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| a/d type touch key mcu BS84B08A-3/bs84c12a-3 revision: v1.00 date: ? a ? 0 ?? ? 01 ? ? a ? 0 ?? ? 01 ?
rev. 1.00 ? ? a ? 0 ?? ? 01 ? rev. 1.00 ? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu table of contents eates cpu features ......................................................................................................................... 6 peripheral features ................................................................................................................. 6 general description ........................................................................................ 7 selection table ................................................................................................. 8 block diagram .................................................................................................. 8 pin assignment ........... ..................................................................................... 9 pin descriptions ............................................................................................ 10 absolute ?aximum ratings .......................................................................... 1? a.c. characteristics ....................................................................................... 1? d.c. characteristics ....................................................................................... 1? adc electrical characteristics ... .................................................................. 14 power-on reset characteristics ........... ........................................................ 15 s?stem architecture ...................................................................................... 16 clocking and pipelining ......................................................................................................... 16 program counter ................................................................................................................... 17 stack ..................................................................................................................................... 18 arithmetic and logic unit C alu ........................................................................................... 18 flash program ?emor? ................................................................................. 19 structure ................................................................................................................................ 19 special vectors ..................................................................................................................... 19 look-up table ............. ........................................................................................................... ? 0 table program example ........................................................................................................ ? 1 in circuit programming ......................................................................................................... ?? ra? data ?emor? ......................................................................................... ?? structure ................................................................................................................................ ?? special function register description ........................................................ ?? indirect addressing registers C iar0 ? iar1 ......................................................................... ?? ? emor ? pointers C ? p0 ? ? p1 .............................................................................................. ? 5 bank pointer C bp ................................................................................................................. ? 6 accumulator C acc ............................................................................................................... ? 6 program counter low register C pcl .................................................................................. ? 7 look-up table registers C tblp ? tbhp ? tblh ..................................................................... ? 7 status register C status .................................................................................................... ? 7 rev. 1.00 ? ?a? 0?? ?01? rev. 1.00 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu eeprom data memory ........... ....................................................................... 29 eepro ? data ? emor ? structure ........................................................................................ ? 9 eepro ? registers ............ .................................................................................................. ? 9 reading data from the eepro ? ........................................................................................ ? 1 writing data to the eepro ? ................................................................................................ ? 1 write protection ..................................................................................................................... ? 1 eepro ? interrupt ............. ................................................................................................... ? 1 programming considerations ............. ................................................................................... ?? oscillator ........................................................................................................ 33 oscillator overview ............. .................................................................................................. ?? system clock confgurations ................................................................................................ ?? internal rc oscillator C hirc ............. .................................................................................. ? 4 internal ?? khz oscillator C lirc ........................................................................................... ? 4 operating modes and system clocks ......................................................... 34 s ? stem clocks ...................................................................................................................... ? 4 s ? stem operation ? odes ...................................................................................................... ? 5 control register .................................................................................................................... ? 6 operating ? ode switching ................................................................................................... ? 8 nor ? al ? ode to slow ? ode switching ........................................................................... ? 9 slow ? ode to nor ? al ? ode switching .......................................................................... ? 9 entering the sleep ? ode .................................................................................................... ? 9 entering the idle0 ? ode ...................................................................................................... ? 9 entering the idle1 ? ode ...................................................................................................... 40 standb ? current considerations ........................................................................................... 40 wake-up ................................................................................................................................ 41 watchdog timer ........... .................................................................................. 42 watchdog timer clock source .............................................................................................. 4 ? watchdog timer control register ............. ............................................................................ 4 ? watchdog timer operation ................................................................................................... 4 ? reset and initialisation .................................................................................. 44 reset functions ............. ....................................................................................................... 44 reset initial conditions ......................................................................................................... 47 input/output ports ......................................................................................... 52 i/o register list .................................................................................................................... 5 ? pull-high resistors ................................................................................................................ 5 ? port a wake-up ............. ........................................................................................................ 54 i/o port control registers ..................................................................................................... 54 i/o pin structures .................................................................................................................. 56 programming considerations ............. ................................................................................... 57 rev. 1.00 4 ? a ? 0 ?? ? 01 ? rev. 1.00 5 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu timer/event counter ..................................................................................... 57 confguring the timer/event counter input clock source .................................................... 57 timer register C t ? r ........................................................................................................... 58 timer control register C t ? rc ............................................................................................ 58 timer operation ............. ....................................................................................................... 59 prescaler ............................................................................................................................... 59 programming considerations ............. ................................................................................... 59 analog to digital converter .......... ................................................................ 60 a/d overview ............. ........................................................................................................... 60 a/d converter register description ...................................................................................... 60 a/d converter data registers C adrl ? adrh ..................................................................... 61 a/d converter control registers C adcr0 ? adcr1 ? acerl ............................................... 61 a/d operation ....................................................................................................................... 64 a/d input pins ............. .......................................................................................................... 65 summar ? of a/d conversion steps ............. .......................................................................... 66 programming considerations ............. ................................................................................... 67 a/d transfer function ............. .............................................................................................. 67 a/d programming examples ................................................................................................. 68 touch key function ...................................................................................... 70 touch ke ? structure .............................................................................................................. 70 touch key register defnition ............................................................................................... 70 touch ke ? operation ............................................................................................................. 76 touch ke ? interrupt ............................................................................................................... 78 programming considerations ............. ................................................................................... 79 serial interface module C sim ...................................................................... 79 spi interface ........................................................................................................................ 79 spi interface operation ........................................................................................................ 79 spi registers ............. ........................................................................................................... 80 spi communication ............................................................................................................. 8 ? i ? c interface ............ ............................................................................................................. 85 i ? c interface operation ......................................................................................................... 85 i ? c registers ......................................................................................................................... 86 i ? c bus communication ....................................................................................................... 90 i ? c bus start signal .............................................................................................................. 91 slave address ...................................................................................................................... 91 i ? c bus read/write signal ................................................................................................... 91 i ? c bus slave address acknowledge signal ........................................................................ 91 i ? c bus data and acknowledge signal ............ .................................................................... 9 ? i ? c time-out control .............................................................................................................. 9 ? rev. 1.00 4 ?a? 0?? ?01? rev. 1.00 5 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu interrupts ........................................................................................................ 94 interrupt registers ................................................................................................................. 94 interrupt operation ................................................................................................................ 96 external interrupt ............. ...................................................................................................... 97 time base interrupt ............................................................................................................... 97 timer/event counter interrupt ............................................................................................... 98 eepro ? interrupt ............. ................................................................................................... 98 touch ke ? interrupt ............................................................................................................... 99 si ? interrupt ......................................................................................................................... 99 a/d converter interrupt ......................................................................................................... 99 interrupt wake-up function .................................................................................................. 99 programming considerations ............. ................................................................................. 100 application circuits ........... .......................................................................... 100 instruction set .............................................................................................. 101 introduction ......................................................................................................................... 101 instruction timing ................................................................................................................ 101 ? oving and transferring data ............................................................................................. 101 arithmetic operations .......................................................................................................... 101 logical and rotate operation ............................................................................................. 10 ? branches and control transfer ........................................................................................... 10 ? bit operations ..................................................................................................................... 10 ? table read operations ....................................................................................................... 10 ? other operations ............. .................................................................................................... 10 ? instruction set summary .......... .................................................................. 103 table conventions ............................................................................................................... 10 ? instruction defnition ................................................................................... 105 package information .................................................................................... 114 16-pin nsop (150mil) outline dimensions .......................................................................... 115 16-pin ssop (150mil) outline dimensions .......................................................................... 116 ? 0-pin ssop (150mil) outline dimensions .......................................................................... 118 ? 4-pin sop ( ? 00mil) outline dimensions ............................................................................ 119 ? 4-pin ssop (150mil) outline dimensions ......................................................................... 1 ? 0 ? 8-pin sop ( ? 00mil) outline dimensions ........................................................................... 1 ? 1 ? 8-pin ssop (150mil) outline dimensions ......................................................................... 1 ?? rev. 1.00 6 ? a ? 0 ?? ? 01 ? rev. 1.00 7 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu features cpu features ? operating v oltage: f sys = 8m hz: 2. 7v~5.5v f sys = 12m hz: 2.7v~5.5v f sys = 16m hz: 4.5v~5.5v ? up to 0.2 5 s instruction cycle with 16 mhz system clock at v dd =5v ? fully integrated 8/12 touch key functions -- require no external components ? power down and wake-up functions to reduce power consumption ? fully integrated low and high speed internal oscillators low speed C 32khz high speed C 8mhz, 12mhz, 16mhz ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 6 -level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 3 k16 ~ 4k16 ? ram data memory: 2888 ~ 3848 ? eeprom memory: 648 ? watchdog t imer function ? u p to 26 bidirectional i/o lines ? external interrupt line shared with i/o pin ? single 8-bit t imer/event counter ? single t ime-base function for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? i 2 c and spi interfaces ? low voltage reset function ? 8/12 touch key functions ? high current led driver rev. 1.00 6 ?a? 0?? ?01? rev. 1.00 7 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu general description these devices are a series of flash memory a/d type 8-bit high performance risc architecture microcontrollers with fully integrated touch key functions. w ith all touch key functions provided internally and with the convenience of flash memory multi-programming features, this device range has a ll the features to offer designers a reliable and easy m eans of i mplementing t ouch keyes within their products applications. analog feature include a multi-chan nel 12-bit a/d converter . protectiv e features such as an internal watchdog t imer and low v oltage reset coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. the t ouch ke y func tions a re ful ly i ntegrated c ompletely e liminating t he ne ed for e xternal components. in addition to the fash program memory , other memory includes an area of ram data memory as well as an area of eep rom memory for storage of non-volatile data such as serial numbers, calibration data etc. all d evices i nclude f ully i ntegrated l ow a nd h igh sp eed o scillators wh ich r equire n o e xternal components for their implementation. t he ability to operate and switch dynamically between a range of operating modes using dif ferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. easy communication with the outside world is provided using the internal i 2 c and spi inter faces, while the inclusion of fexible i/o programming features, timer/event counter and many other features further enhance device functionality and fexibility. these touch key devices will find excellent use in a huge range of modern t ouch key product applications such as instrumentatio n, household appliances, electronic ally controlled tools to name but a few. rev. 1.00 8 ? a ? 0 ?? ? 01 ? rev. 1.00 9 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu selection table most features are common to all devices , the main distinguishing feature is the number of i/os and touch keys. the following table summarises the main features of each device. part no. internal clock v dd system clock program memory data memory data eeprom i/o high current led output a/d 8-bit timer time base touch key spi/ i 2 c lvr stack package bs84b08 a- ? 8 ? hz 1 ? ? hz 16 ? hz ? .7v ~ 5.5v 8 ? hz ~ 16 ? hz ? k16 ? 888 648 ?? ?? 1 ? -bit 8 1 1 8 1 ? .55v 6 16nsop/ssop ? 0sop/ssop ? 4sop/ssop bs8 4c1 ? a- ? 8 ? hz 1 ? ? hz 16 ? hz ? .7v ~ 5.5v 8 ? hz ~ 16 ? hz 4k16 ? 848 648 ? 6 ? 6 1 ? - bit8 1 1 1 ? 1 ? .55v 6 ? 0sop/ssop ? 4sop/ssop ? 8sop/ssop block diagram ? ? ? ? ? ? - ? - ? ? ? ? ? ? ? ? ? ?? ? ? - ? rev. 1.00 8 ?a? 0?? ?01? rev. 1.00 9 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu pin assignment ?4 ?? ?? ?1 ?0 19 18 17 16 15 14 1? 1 ? ? 4 5 6 7 8 9 10 11 1? bs 84 b 08 a-3 24 sop -a/ ssop -a pb 0/ ke? 1 pb 1/ ke? ? pb ?/ ke? ? pb ?/ ke? 4 pb 4/ ke? 5 pb 5/ ke? 6 vss vdd pa ?/ sck / scl pa 0/ sdi / sda pa 1/ sdo pa 7 pa ?/ scs pa 4/ int pd 0/ an 0/v ref pd ?/ an ? pd 5/ an 5 pd 4/ an 4 pd 7/ an 7 pd 6/ an 6 pd ?/ an ? pb 6/ ke? 7 pb 7/ ke? 8 pd 1/ an 1 ?0 19 18 17 16 15 14 1? 1? 11 1 ? ? 4 5 6 7 8 9 10 bs 84 c 12 a-3 20 sop -a/ ssop -a pb 0/ ke? 1 pb 1/ ke? ? pb ?/ ke? ? pb ?/ ke? 4 pb 4/ ke? 5 pb 5/ ke? 6 pd 0/ an 0/v ref vss vdd pa ?/ sck / scl pa 0/ sdi / sda pa 1/ sdo pa 7 pa ?/ scs pa 4/ int pd 5/ an 5 pd 4/ an 4 pb 6/ ke? 7 pb 7/ ke? 8 pd 1/ an 1 ?0 19 18 17 16 15 14 1? 1? 11 1 ? ? 4 5 6 7 8 9 10 bs 84 b 08 a-3 20 sop -a/ ssop -a vss vdd pa ?/ sck / scl pa 0/ sdi / sda pa 1/ sdo pa 7 pa ?/ scs pa 4/ int pb 0/ ke? 1 pb 1/ ke? ? pb ?/ ke? ? pb ?/ ke? 4 pb 4/ ke? 5 pb 5/ ke? 6 pd 0/ an 0/v ref pd 7/ an 7 pd 6/ an 6 pb 6/ ke? 7 pb 7/ ke? 8 pd 1/ an 1 16 15 14 1? 1? 11 10 9 1 ? ? 4 5 6 7 8 bs 84 b 08 a-3 16 nsop -a/ ssop -a pb 0/ ke? 1 pb 1/ ke? ? pb ?/ ke? ? pb ?/ ke? 4 pb 4/ ke? 5 pb 5/ ke? 6 pd 0/ an 0/v ref vss vdd pa ?/ sck / scl pa 0/ sdi / sda pa 1/ sdo pa 7 pa ?/ scs pa 4/ int pd 1/ an 1 ?4 ?? ?? ?1 ?0 19 18 17 16 15 14 1? 1 ? ? 4 5 6 7 8 9 10 11 1? bs 84 c 12 a-3 24 sop -a/ ssop -a pb 0/ ke? 1 pb 1/ ke? ? pb ?/ ke? ? pb ?/ ke? 4 pb 4/ ke? 5 pb 5/ ke? 6 pc 0/ ke? 9 pc 1/ ke? 10 vss vdd pa ?/ sck / scl pa 0/ sdi / sda pa 1/ sdo pa 7 pa ?/ scs pa 4/ int pd 0/ an 0/v ref pd 5/ an 5 pd 4/ an 4 pd 7/ an 7 pd 6/ an 6 pb 6/ ke? 7 pb 7/ ke? 8 pd 1/ an 1 ?8 ?7 ?6 ?5 ?4 ?? ?? ?1 ?0 19 18 17 16 15 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 vss vdd pb 0/ ke? 1 pb 1/ ke? ? pb ?/ ke? ? pb ?/ ke? 4 pb 4/ ke? 5 pb 5/ ke? 6 pc 0/ ke? 9 pc 1/ ke? 10 bs 84 c 12 a-3 28 sop -a/ ssop -a pa ?/ sck / scl pa 0/ sdi / sda pa 1/ sdo pd ?/ an ? pd 0/ an 0/v ref pd 5/ an 5 pd 4/ an 4 pd 7/ an 7 pd 6/ an 6 pd ?/ an ? pa7 pa ?/ scs pc ?/ ke? 11 pc ?/ ke? 1? pa 4/ int pb 6/ ke? 7 pb 7/ ke? 8 pd 1/ an 1 rev. 1.00 10 ? a ? 0 ?? ? 01 ? rev. 1.00 11 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu pin descriptions the function of each pin is listed in the following table s , however the details behind how each pin is confgured is contained in other sections of the datasheet. BS84B08A-3 pin name function opt i/t o/t description pa0/ sdi/sda pa0 pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. sdi st spi data input sda st n ? os i ? c data pa1/ sdo pa1 pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. sdo si ? c 0 c ? os spi data output pa ? / sck/scl pa ? pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. sck si ? c0 st c ? os spi serial clock scl si ? c0 st n ? os i ? c clock pa ? /scs pa ? pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. scs si ? c0 st c ? os spi slave select pa4/ int pa4 pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. int integ st external interrupt pa7 pa7 pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. pb0/key1~ pb ? /key4 pb0 ~pb ? pbpu st c ? os general purpose i/o. register enabled pull-up. key1~ key4 tk ? 0c1 nsi touch ke ? inputs pb4/key5~ pb7/key8 pb4~pb7 pbpu st c ? os general purpose i/o. register enabled pull-up. key5~ key8 tk ? 1c1 nsi touch ke ? inputs pd0/an0/ vref pd0 pdpu st c ? os general purpose i/o. register enabled pull-up. an0 acerl an adc input vref adcr1 an adc reference input pd1/an1~ pd7/an7 pd1~pd7 pdpu st c ? os general purpose i/o. register enabled pull-up. an1~an7 acerl an adc input vdd vdd pwr power suppl ? vss vss pwr ground legend : i/t : input type o/t : output type op: optional by register selection an: analog input pin pwr : power st : schmitt t rigger input cmos : cmos output nmos : nmos output nsi: no n-standard input rev. 1.00 10 ?a? 0?? ?01? rev. 1.00 11 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu bs84c12a-3 pin name function opt i/t o/t description pa0/ sdi/sda pa0 pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. sdi st spi data input sda st n ? os i ? c data pa1/ sdo pa1 pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. sdo si ? c 0 c ? os spi data output pa ? / sck/scl pa ? pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. sck si ? c0 st c ? os spi serial clock scl si ? c0 st n ? os i ? c clock pa ? /scs pa ? pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. scs si ? c0 st c ? os spi slave select pa4/ int pa4 pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. int integ st external interrupt pa7 pa7 pa wu pa pu st c ? os general purpose i/o. register enabled pull-up and wake-up. pb0/key1~ pb ? /key4 pb0 ~pb ? pbpu st c ? os general purpose i/o. register enabled pull-up. key1~ key4 tk ? 0c1 nsi touch ke ? inputs pb4/key5~ pb7/key8 pb4~pb7 pbpu st c ? os general purpose i/o. register enabled pull-up. key5~ key8 tk ? 1c1 nsi touch ke ? inputs pc0/key9~ pc ? / key1 ? pc0 ~pc ? pcpu st c ? os general purpose i/o. register enabled pull-up. key9~ key1 ? tk ?? c1 nsi touch ke ? inputs pd0/an0/ vref pd0 pdpu st c ? os general purpose i/o. register enabled pull-up. an0 acerl an adc input vref adcr1 an adc reference input pd1/an1~ pd7/an7 pd1~pd7 pdpu st c ? os general purpose i/o. register enabled pull-up. an1~an7 acerl an adc input vdd vdd pwr power suppl ? vss vss pwr ground legend : i/t : input type o/t : output type op: optional by register selection an: analog input pin pwr : power st : schmitt t rigger input cmos : cmos output nmos : nmos output nsi: no n-standard input rev. 1.00 1 ? ? a ? 0 ?? ? 01 ? rev. 1.00 1? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i oh t otal .............. ...................................................................................................................... -80ma i ol t otal .............. ....................................................................................................................... 80ma total power dissipation .............. .......................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. a.c. characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd conditions f sys s ? stem clock (hirc) ? v/5v 7d - ? % 8 + ? % ? hz - ? % 1 ? + ? % ? hz - ? % 16 + ? % ? hz f ti ? er timer input pin frequenc ? ? . 7v~5.5v 8 ? hz ? .7 v~5.5v 1 ? ? hz 4.5v~5.5v 16 ? hz f lirc s ? stem clock ( ?? khz) 5v ta = ? - ? % ?? + ? % khz t int interrupt pulse width 1 5 10 v t lvr low voltage width to reset 1 ? 0 ? 40 480 v t eerd eepro ? read time 1 ? 4 t sys t eewr eepro ? write time 1 ? 4 ms t sst s ? stem start-up timer period (wake-up from halt) f sys =hirc 15~16 ? 0 t sys f sys =lirc 1~ ? ? note: 1. t sys = 1/f sys 2 . t o maintain the accuracy of the internal hirc oscillator frequency , a 0.1f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. 3. 16mhz can not be used when the supply voltage is below 3v. rev. 1.00 1? ?a? 0?? ?01? rev. 1.00 1 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu d.c. characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (hirc) f sys = 8 ? hz ? .7 5.5 v f sys = 1 ? ? hz ? .7 5.5 v f sys = 16 ? hz 4.5 5.5 v i dd1 operating current (hirc ? f sys =f h ? f s =f sub =f lirc ) ? v no load ? f h = 8 ? hz adc off ? wdt enable 1. ? 1.8 ma 5v ? . ? ? . ? ma ? v no load ? f h = 1 ? ? hz adc off ? wdt enable 1.6 ? .4 ma 5v ? . ? 5.0 ma ? v no load ? f h = 16 ? hz adc off ? wdt enable ? .0 ? .0 ma 5v 4.0 6.0 ma i dd ? operating current (hirc ? f sys =f l ? f s =f sub =f lirc ) ? v no load ? f h = 1 ? ? hz ? f l = f h / ?? adc off ? wdt enable 1. ? ? .0 ma 5v ? . ? ? . ? ma ? v no load ? f h = 1 ? ? hz ? f l = f h /4 ? adc off ? wdt enable 1.0 1.5 ma 5v 1.8 ? .7 ma ? v no load ? f h = 1 ? ? hz ? f l = f h /8 ? adc off ? wdt enable 0.9 1.4 ma 5v 1.6 ? .4 ma ? v no load ? f h = 1 ? ? hz ? f l = f h /16 ? adc off ? wdt enable 0.8 1. ? ma 5v 1.5 ? . ? ma ? v no load ? f h = 1 ? ? hz ? f l = f h / ??? adc off ? wdt enable 0.8 1. ? ma 5v 1.5 ? . ? ma ? v no load ? f h = 1 ? ? hz ? f l = f h /64 ? adc off ? wdt enable 0.8 1. ? ma 5v 1.5 ? . ? ma i dd ? operating current (lirc ? f sys =f l= f lirc ? f s =f sub =f lirc ) ? v no load ? adc off ? wdt enable ? lvr enable 50 100 a 5v 70 150 a i stb1 idle ? ode standb ? current (hirc ? f sys =f h ? f s =f sub =f lirc ) ? v no load ? s ? stem halt ? adc off ? wdt enable ? f sys = 1 ? ? hz 0.9 1.4 ma 5v 1.4 ? .1 ma i stb ? idle ? ode standb ? current (hirc ? f sys =off ? f s =f sub =f lirc ) ? v no load ? s ? stem halt ? adc off ? wdt enable ? f sys = 1 ? ? hz ? lvr enable 40 80 a 5v 50 100 a i stb ? idle ? ode standb ? current (hirc ? f sys = f l ? f s =f sub =f lirc ) ? v no load ? s ? stem halt ? adc off ? wdt enable ? f sys = 1 ? ? hz /64 0.7 1.1 ma 5v 1.4 ? .1 ma i stb4 idle ? ode standb ? current (hirc ? f sys =off ? f s =f sub =f lirc ) ? v no load ? s ? stem halt ? adc off ? wdt enable ? f sys = 1 ? ? hz /64 ? lvr enable 40 80 a 5v 50 100 a rev. 1.00 14 ? a ? 0 ?? ? 01 ? rev. 1.00 15 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu symbol parameter test conditions min. typ. max. unit v dd conditions i stb5 idle ? ode standb ? current (lirc ? f sys =f l =f lirc ? f s =f sub =f lirc ) ? v no load ? s ? stem halt ? adc off ? wdt enable ? f sys = ?? k hz 1.9 4.0 a 5v ? . ? 7.0 a i stb6 idle ? ode standb ? current (lirc ? f sys =off ? f s =f sub =f lirc ) ? v no load ? s ? stem halt ? adc off ? wdt enable ? f sys = ?? k hz ? lvr enable 40 80 a 5v 50 100 a i stb7 sleep ? ode standb ? current (hirc ? f sys =off ? f s =f sub =f lirc ) ? v no load ? s ? stem halt ? adc off ? wdt enable ? f sys = 1 ?? hz ? lvr enable 40 80 a 5v 50 100 a i stb8 sleep ? ode standb ? current (lirc ? f sys =off ? f s =f sub =f lirc ) ? v no load ? s ? stem halt ? adc off ? wdt enable ? f sys = ?? k hz 1. ? ? .0 a 5v ? .4 5.0 a v il input low voltage for i/o ports or input pins 5v 0 1.5 v 0 0. ? v dd v v ih input high voltage for i/o ports or input pins 5v ? .5 5.0 v 0.8v dd v dd v v lvr low voltage reset voltage lvr enable ? ? .55v -5% ? .55 +5% v i lvr low voltage reset current lvr enable 6 ? 90 a i ol sink current for i/o port ? v v ol =0.1v dd 8 16 ma 5v v ol =0.1v dd 16 ?? ma i oh source current for i/o port ? v v oh =0.9v dd - ? .75 -7.5 ma 5v v oh =0.9v dd -7.5 -15 ma r ph pull-high resistance for i/o ports ? v ? 0 60 100 k 5v 10 ? 0 50 k adc electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d converter operating voltage ? . 7 5.5 v v adi a/d converter input voltage 0 v ref v v ref a/d converter reference voltage ? a v dd v v bg reference voltage - ? % 1.19 + ? % v dnl1 differential non-linearit ? ? v v ref =av dd =v dd t adck =0.5s ta= ? 5 c - ? .0 + ? .0 lsb 5v dnl ? differential non-linearit ? ? v v ref =av dd =v dd t adck =0.5s ta = - ? 0 c ~ 85c -4.0 +4.0 lsb 5v dnl ? differential non-linearit ? ? v v ref =av dd =v dd t adck =0.5s ta = -40c ~ - ? 0 c -8.5 +8.5 lsb 5v rev. 1.00 14 ?a? 0?? ?01? rev. 1.00 15 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu symbol parameter test conditions min. typ. max. unit v dd conditions inl1 integral non-linearit ? ? v v ref =av dd =v dd t adck =0.5s ta= ? 5 c -4.0 +4.0 lsb 5v inl ? integral non-linearit ? ? v v ref =av dd =v dd t adck =0.5s ta = - ? 0 c ~ 85c -4. ? +4. ? lsb 5v inl ? integral non-linearit ? ? v v ref =av dd =v dd t adck =0.5s ta = -40c ~ - ? 0 c -8.5 +8.5 lsb 5v i adc additional power consumption if a/d converter is used ? v no load (t adck =0.5s ) 0.9 1. ? 5 ma 5v no load (t adck =0.5s ) 1. ? 1.8 ma t adck a/d converter clock period 0.5 100 s t adc a/d conversion time (include sample and hold time) 1 ? -bit adc 16 t adck t ads a/d converter sampling time 4 t adck t on ? st a/d converter on-to-start time ? s t bgs v bg turn on stable time ? 00 s power-on reset characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start voltage to ensure power-on reset 100 mv rr vdd v dd raising rate to ensure power-on reset 0.0 ? 5 v/ms t por ? inimum time for v dd sta ? s at v por to ensure power-on reset 1 ms rev. 1.00 16 ? a ? 0 ?? ? 01 ? rev. 1.00 17 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantag e of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal regis ters are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility . this makes th ese device s suitable for low-cost, high-volume production for controller applications. clocking and pipelining the mai n system clock, deri ved from eit her a high or low speed oscilla tor is subdivide d into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. ? ? ? ? ? ? ?? system clock and pipelining rev. 1.00 16 ?a? 0?? ?01? rev. 1.00 17 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register bs84b08a- ? pc10~pc8 pcl7~pcl0 bs84c1 ? a- ? pc10~pc8 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jum ps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. rev. 1.00 18 ? a ? 0 ?? ? 01 ? rev. 1.00 19 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost. arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti rev. 1.00 18 ?a? 0?? ?01? rev. 1.00 19 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. by using the appropriate programming tools, these flash device s of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the program memory has a capaci ty of 3k16 or 4 k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. t able data, which c an b e se tup i n a ny l ocation wi thin t he pro gram me mory, i s a ddressed b y a se parate t able pointer register. device capacity banks bs84b08a- ? ? k16 0 ? 1 bs84c1 ? a- ? 4k16 0 ? 1 ?? special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. program memory structure rev. 1.00 ? 0 ? a ? 0 ?? ? 01 ? rev. 1.00 ?1 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd c [m] or t abrdl[m] instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table. instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrd c [m] @10 @9 @8 @7 @6 @5 @4 @ ? @ ? @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @ ? @ ? @1 @0 table location note: b 10~b0 : table location bits @7~@0: t able pointer (tblp) bits @10~@8 : t able pointer (tb h p) bits rev. 1.00 ?0 ?a? 0?? ?01? rev. 1.00 ? 1 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is f 00h which refers to the start address of the last page within the 4 k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address f 06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd c [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrd c [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,0 f h ; initialise high table pointer mov tbhp,a : : tabrd c tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address f 06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd c tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address f 05h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org f 00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : rev. 1.00 ?? ? a ? 0 ?? ? 01 ? rev. 1.00 ?? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4 -pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek write pins mcu programming pins function icpda pa 0 serial address and data -- read/write icpck pa ? programming serial clock vdd vdd power suppl ? (5.0v) vss vss ground during the programming process, the user must there take care to ensure that no other outputs are connected to these two pins. the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for t he c lock. t wo a dditional l ines a re re quired for t he powe r suppl y. t he t echnical de tails regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process the p a0 and p a2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. note: * may be resistor or capacitor. the resistance of * must be greater than 1k? or the capacitance of * must be less than 1nf. rev. 1.00 ?? ?a? 0?? ?01? rev. 1.00 ?? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locatio ns within this area are read and write accessible under program control. the overall data memory is subdivided into several banks for the devices . the special purpose data memory registers are accessib le in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. device capacity bank 0 bank 1 bank 2 bs84b08a- ? ? 888 60h~ffh 80h~ffh bs84c1 ? a- ? ? 848 60h~ffh 80h~ffh 80h~dfh general purpose data memory special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. rev. 1.00 ? 4 ? a ? 0 ?? ? 01 ? rev. 1.00 ?5 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ????????? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?????????? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? special purpose data memory rev. 1.00 ?4 ?a? 0?? ?01? rev. 1.00 ? 5 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org00h start : mov a , 04h ; setup size of block mov block , a mov a , offset adres1 ; accumulator loaded with frst ram address mov mp0 , a ; setup memory pointer with frst ram address loop : clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. rev. 1.00 ? 6 ? a ? 0 ?? ? 01 ? rev. 1.00 ?7 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu bank pointer C bp depending upon which device is used, the program and data memory are divided into several banks , bank0, bank1 and bank2 . selecting the required data memory area is achieved using the bank pointer. bit 0 and bit 1 of the bank pointer are used to select data memory banks 0~ 2 . the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addre ssing the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from bank 1 must be implemented using indirect a ddressing. as both the program memory and data memory share the same bank pointer register , care must be taken during programming. bp register C BS84B08A-3 bit 7 6 5 4 3 2 1 0 name d ? bp0 r/w r/w por 0 b it 7 ~ 2 unimplemented, read as 0 b it 1~0 dmbp0 : select data memory banks 0 : bank 0 1: bank 1 bp register C bs84c12a-3 bit 7 6 5 4 3 2 1 0 name d ? bp 1 d ? bp0 r/w r/w r/w por 0 0 b it 7 ~ 2 unimplemented, read as 0 b it 1~0 dmbp1 ~ dmbp0 : select data memory banks 00 : bank 0 0 1: bank 1 10 : bank 2 1 1: reserved accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user - defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. rev. 1.00 ?6 ?a? 0?? ?01? rev. 1.00 ? 7 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. rev. 1.00 ? 8 ? a ? 0 ?? ? 01 ? rev. 1.00 ?9 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 unknown b it 7 ~ 6 unimplemented, read as 0 b it 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. b it 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction b it 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. b it 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero b it 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction b it 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. rev. 1.00 ?8 ?a? 0?? ?01? rev. 1.00 ? 9 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu eeprom data memory one of the s pecial features in the device is its internal eep rom d ata m emory. eep rom, w hich stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory , with data retention even when its power supply is removed. by incorporating this kind of data mem ory, a whol e new host of appl ication possibi lities are ma de avail able to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is up to 648 bits. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address bs84b08a- ? 648 00h~ ? fh bs84c1 ? a- ? 648 00h~ ? fh eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special functi on regist er. the eec re gister however , be ing located in bank1, cannot be di rectly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d5 d4 d ? d ? d1 d0 eed d7 d6 d5 d4 d ? d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por unknown b it 7 ~ 6 unimplemented, read as 0 b it 5 ~ 0 data eeprom address data eeprom address bit 5 ~ bit 0 rev. 1.00 ? 0 ? a ? 0 ?? ? 01 ? rev. 1.00 ?1 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 4 unimplemented, read as 0 b it 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. b it 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. b it 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. b it 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set hi gh by the applicat ion program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. rev. 1.00 ?0 ?a? 0?? ?01? rev. 1.00 ? 1 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom to wr ite da ta t o t he e eprom, t he wr ite e nable bi t, w ren, i n t he e ec re gister m ust frst be se t high to enable the w rite function. the eep rom addres s of the data to be w ritten mus t then be placed in the eea register and the data placed in the eed register . if the wr bit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fni shed c an be i mplemented e ither by pol ling t he w r bi t i n t he e ec re gister or by usi ng t he eeprom i nterrupt. w hen t he wr ite c ycle t erminates, t he w r b it wi ll b e a utomatically c leared t o zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered- on the w rite enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register . when an eeprom write cycle ends, the def request fag will be set. if the global, eeprom is enabled and the stack is not full, a jump to the associated interrupt vector will take place. when the interrupt is serviced, t he e eprom i nterrupt fa g will a utomatically reset. mo re d etails c an b e o btained i n t he interrupt section. rev. 1.00 ?? ? a ? 0 ?? ? 01 ? rev. 1.00 ?? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. programming examples ? reading data from the eeprom C polling method 0293520b56 hhhdh 029 029 hhlh03 02903 03lhlh 029 hd3lh 0293 6,5 h51elhdehhdhdl 6,5 d5hdfhh5el back: 6,5 fkhfhdffhh -03. /5,5 ldeh3520lh /53 029 ; move read data to register 0295b ? writing data to the eeprom C polling method /5 0, 0293520b56 hhhdh 029 0293520b hhhdd 029 029 hhlh03 02903 03lhlh 029 hd3lh 0293 6,5 h:51elhdehlhhdl 6,5 d:lhfhh:5el 60, back: 6,5 ; check for write cycle end -03. /5,5 ldeh3520lh /53 rev. 1.00 ?? ?a? 0?? ?01? rev. 1.00 ?? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimization can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for the watchdog t imer and t ime base interrupts. f ully integrated inte rnal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillators p rovide h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capabilit y of dynamically switching between fast and slow system clock, the device has the fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. internal high speed rc hirc 8/1 ? /16 ? hz internal low speed rc lirc ?? khz oscillator types system clock confgurations there are t wo m ethods of generat ing t he syst em cl ock, a high spee d osci llator and a low spee d oscillator. the high speed oscillator is the internal 8mhz, 1 2mhz, 16 mhz rc oscillator . the low speed os cillator is the internal 32khz (lirc) oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. the actua l source clock used for the high speed and the low speed oscillators is chosen via registers . the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register . note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no- oscillator selection for either the high or low speed oscillator. ? ? ? ?? ? ? ? - ? ? system clock confgurations rev. 1.00 ? 4 ? a ? 0 ?? ? 01 ? rev. 1.00 ?5 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a power on default frequency of 8 mhz but can be selected to be either 8mhz, 12mhz or 16mhz using the hircs1 and hircs0 bits in the ctrl register . device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimi sed. internal 32khz oscillator C lirc the internal 32khz system oscillator is the low frequency oscillator . it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. after power on this lirc oscillator will be permanently enabled; there is no provision to disable the oscillator using . operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the main system clock, can come from either a high frequency , f h , or low frequency , f sub , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register . both the high and low speed system clocks are sourced from internal rc oscillators. ? ? ? ? ? ? ?- ? ? ? ?? ? ? ? ?? ? ?? ? ? ? ? ? ? system clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. rev. 1.00 ?4 ?a? 0?? ?01? rev. 1.00 ? 5 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu system operation modes there a re five d ifferent m odes o f o peration f or t he m icrocontroller, e ach o ne wi th i ts o wn special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep , idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f sub f s n or ? al mode on f h ~f h /64 on on slow mode on f sub on on ilde0 mode off off on on idle1 mode off on on on sleep mode off off on on normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the high speed oscillator , hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod regis ter. a lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock so urce. t he c lock so urce u sed wi ll b e f rom f sub . r unning t he m icrocontroller i n t his m ode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep mode the cpu will be stopped. however the f sub clocks will continue to run the w atchdog t imer will continue to operate . idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl register i s l ow. in the idle 0 mode the system oscillator will be stop and will therefore be inhibited from driving the cpu but some peripheral functions will remain operational such as the w atchdog t imer, t imer/event counter . idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod registe r is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be the high speed or low speed system oscillator . in the idle1 mode the w atchdog t imer clock, f s , will be on. t he source comes from f sub then f s will be on. rev. 1.00 ? 6 ? a ? 0 ?? ? 01 ? rev. 1.00 ?7 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu control register the smod register is used to control the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 b it 7 ~ 5 cks2 ~ cks0 : the system clock selection when hlclk is 0 000: f sub (f lirc ) 001: f sub (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0. b it 3 lto : lirc system osc sst ready fag 0: not ready 1: ready this is the low speed system oscill ator sst ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will change to a high level after 1~2 cycles. b it 2 hto : hirc system osc sst ready fag 0: not ready 1: ready this is the high speed system oscillator sst ready fag which indicates when the high speed system oscillator is stable after a wake-up has occurred. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the h igh sp eed sy stem o scillator i s stable. t herefore t his fag wi ll a lways b e r ead a s 1 by the application program after device power -on. the fag will be low when in the sleep or idle 0 mode but after power on reset or a wake-up has occurred, the fag will change to a high level after 15~16 clock cycles if the hirc oscillator is used. b it 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he idle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o keep t he pe ripheral fun ctions ope rational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. b it 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f sub cloc k is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f sub clock will be selected. when system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched off to conserve power. rev. 1.00 ?6 ?a? 0?? ?01? rev. 1.00 ? 7 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ctrl register bit 7 6 5 4 3 2 1 0 name fsyson hircs1 hircs0 lvrf lrf wrf r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 unknown b it 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6 unimplemented, read as 0. bit 5~4 hircs1~hircs0 : high frequency clock select 0 0: 8mhz 01 : 16 mhz 10: 12 mhz 11: 8 mhz bit 3 unimplemented, read as 0. b it 2 lvrf : lvr function reset fag 0: n ot occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. b it 1 lrf : lvrc control register software reset fag 0: n ot occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to 0 by the application program. b it 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. rev. 1.00 ? 8 ? a ? 0 ?? ? 01 ? rev. 1.00 ?9 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ?? ? ? ?? ? ?? ? ? ?? ? ?? ? operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically al lowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction . when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condit ion of the idl en bit in the smod regi ster and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running . the accompanying fowchart shows what happens when the device moves between the various operating modes. rev. 1.00 ?8 ?a? 0?? ?01? rev. 1.00 ? 9 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se t ting t he hlclk bit to 0 and set ting the cks2~cks0 bits to 000 or 001 in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator . t o switch back to the normal mode, w here the high s peed s ystem os cillator is us ed, the h lclk bit s hould be s et to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto b it i s c hecked. t he a mount o f t ime r equired f or h igh sp eed sy stem o scillator st abilization depends upon which high speed system oscillator type is used. entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the hal t instruction in the application program with the idlen bit in smod register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction , but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruc - tion, but the t ime base and the low frequency f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. rev. 1.00 40 ? a ? 0 ?? ? 01 ? rev. 1.00 41 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the low frequency f sub will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting . ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. ?? ? ?? ? ? ? ?? ? ?? ? ? ? ?? ? ?? ? ? ?? ???? ? ? ? ? ?? ???? ? ? ? ? ?? ???? standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbon d ed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. t hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps . rev. 1.00 40 ?a? 0?? ?01? rev. 1.00 41 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow i f the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, t he actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power-up or executing the clear w atchdog t imer instructions and is set when executing the hal t instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. system oscillator wake-up time (sleep mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hirc 15~16 hirc c ? cles 1~ ? hirc c ? cles lirc 1~ ? lirc c ? cles 1~ ? lirc c ? cles wake-up time rev. 1.00 4 ? ? a ? 0 ?? ? 01 ? rev. 1.00 4? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal fsub clock which is in turn supplied by the lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillato r has an approximate period of 32khz at a supply voltage of 5v . however, it should be noted that this specifed internal clock period can vary with vdd, temperature and process variations. the wdt is always enabled. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable operation . the wdtc register is initiated to 0101001 1b at any res et but keeps unchanged at the wd t time-out occurrence in a power down state. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 b it 7~ 3 we4 ~ we0 : wdt function software control 10101 b or 01010b: en able d other values: reset mcu (reset will be active after 2 ~ 3 lirc clock for debounce time.) if the mcu reset caused by the we [4:0] in wdtc software reset, the wrf fag of ctrl register will be set). b it 2~ 0 ws2 ~ ws0 : wdt t ime - out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub (default) 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub these three bits determine the divis ion ratio of the watchdog timer source clock, which in turn determines the timeout period. rev. 1.00 4? ?a? 0?? ?01? rev. 1.00 4 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ctrl register bit 7 6 5 4 3 2 1 0 name fsyson hircs1 hircs0 lvrf lrf wrf r/w r/w r/w r/w r/w r/w r/w por 0 0 0 x 0 0 unknown b it 7 fsyson : f sys control idle mode describe elsewhere b it 6 unimplemented, read as 0 bit 5 ~ 4 hircs1~hircs0 : high frequency clock select describe elsewhere b it 3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag describe elsewhere bit 1 lrf : lvr control register software reset fag describe elsewhere bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. watchdog timer operation in these devices the w atchdog t imer supplied by the f sub oscillator and is therefore always on. the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instruction will not be executed in the correct manne r, in which case the w atchdog t imer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to enable the wdt function. when the we4~we0 bits value is equal to 01010b or 10101b, the wdt function is enabled. however , if the we4~we0 bits are changed to any other values except 01010b and 10101b, which is caused by the environmental noise, it will reset the microcontroller after 2~3 lirc clock cycles. under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitiali s e a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. four methods can be adopted to clear the contents of the w atchdog t imer. t he frst is a wdt reset, which means a certain value is written into the we4~we0 bit fled except 01010b a nd 10101b, t he second i s usi ng t he w atchdog t imer soft ware c lear i nstructions a nd t he third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. rev. 1.00 44 ? a ? 0 ?? ? 01 ? rev. 1.00 45 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ? ?? ?? ? ?? ? ? - ? ? ? ? watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a microcontroller reset can occur, through events occurring internally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. power-on reset timing chart rev. 1.00 44 ?a? 0?? ?01? rev. 1.00 45 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu low voltage reset C lvr the mi crocontroller cont ains a low volt age reset circui t in order to moni tor the supply volt age of the de vice , which is selected vi a a confgura tion opti on . if the supply voltage of the de vice drops to within a range of 0.9v~ v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set . f or a valid l vr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specifed in the a.c. characteristic s. if the low voltage state does not exceed this value , the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr is set by the l vrc register . if the l vs7~lvs0 bits are changed to some certain values by the environmental noise, the l vr will reset the device after 2~3 lirc clock cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the l vr function will be automatica lly disabled when the device enters the power down mode. low voltage reset timing chart lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 b it 7~0 lvs7 ~ lvs0 : lvr v oltage select control 01010101: 2.55v(default) 00110011: 2.55v 10011001: 2.55v 10101010: 2.55v other values: mcu reset (reset will be active after 2~3 lirc clock for debounce time) note: s/w can write 00h~ffh to control l vr voltage, even to s/w reset mcu. if the mcu reset caused lvrc software reset, the lrf fag of ctrl register will be set. rev. 1.00 46 ? a ? 0 ?? ? 01 ? rev. 1.00 47 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ctrl register bit 7 6 5 4 3 2 1 0 name fsyson hircs1 hircs0 lvrf lrf wrf r/w r/w r/w r/w r/w r/w r/w por 0 0 0 x 0 0 unknown b it 7 fsyson: f sys control idle mode describe elsewhere bit 6 unimplemented, read as 0 bit 5 ~ 4 hircs1~hircs0 : high frequency clock select describe elsewhere bit 3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag describe elsewhere watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a lvr reset except that the watchdog time-out fag t o will be set to 1. wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by the hirc. the t sst is 1~2 clock for the lirc. wdt time-out reset during sleep or idle timing chart rev. 1.00 46 ?a? 0?? ?01? rev. 1.00 47 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 power-on reset u u lvr reset during nor ? al or slow ? ode operation 1 u wdt time-out reset during nor ? al or slow ? ode operation 1 1 wdt time-out reset during idle or sleep ? ode operation note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset ? wdt begins counting timer /event counter timer /event counter will be turned off input/output ports i/o ports will be setup as inputs and an0~an7 as a/d input pins stack pointer stack pointer will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. rev. 1.00 48 ? a ? 0 ?? ? 01 ? rev. 1.00 49 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu BS84B08A-3 register register lvr&power on wdt overfow (normal mode) wdt overfow ( halt mode ) iar0 ---- ---- ---- ---- ---- ---- ? p0 xxxx xxxx xxxx xxxx uuuu uuuu iar1 ---- ---- ---- ---- ---- ---- ? p1 xxxx xxxx xxxx xxxx uuuu uuuu bp ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu tbhp ---- xxxx ---- uuuu ---- uuuu status --00 xxxx --1u uuuu --11 uuuu s ? od 0000 0011 0000 0011 uuuu uuuu ctrl 0-00 -x00 0-00 -x00 u-uu -uuu integ ---- --00 ---- --00 ---- --uu intc0 -000 0000 -000 0000 -uuu uuuu intc1 -000 -000 -000 -000 -uuu -uuu lvrc 0000 0000 0000 0000 u uuu uuuu pa 1--1 1111 1--1 1111 u--u uuuu pac 1--1 1111 1--1 1111 u--u uuuu papu 0--0 0000 0--0 0000 u--u uuuu pawu 0--0 0000 0--0 0000 u--u uuuu wdtc 0101 0011 0101 0011 uuuu uuuu tbc --00 ---- --00 ---- --uu ---- t ? r 0000 0000 0000 0000 uuuu uuuu t ? rc --00 -000 --00 -000 --uu -uuu eea --11 1111 --11 1111 --uu uuuu eed 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 u uuu uuuu pbc 1111 1111 1111 1111 u uuu uuuu pbpu 0000 0000 0000 0000 u uuu uuuu i ? ctoc 0000 0000 0000 0000 uuuu uuuu si ? c0 0000 -00- 0000 -00- uuuu Cuu- si ? c1 1000 0001 1000 0001 uuuu -uuu si ? d 0000 0000 0000 0000 uuuu uuuu si ? c ? --11 1111 --11 1111 --uu uuuu si ? a 0000 0000 0000 0000 u uuu uuuu adrl(adrfs=0) xxxx ---- xxxx ---- uuuu ---- adrl(adrfs=1) xxxx xxxx xxxx xxxx uuuu uuuu adrh(adrfs=0) xxxx xxxx xxxx xxxx uuuu uuuu adrh(adrfs=1) ---- xxxx ---- xxxx ---- uuuu adcr0 0110 0000 0110 0000 uuuu uuuu adcr1 00-0 -000 00-0 -000 uu-u -uuu acerl 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 u uuu uuuu pdc 1111 1111 1111 1111 u uuu uuuu pdpu 0000 0000 0000 0000 u uuu uuuu rev. 1.00 48 ?a? 0?? ?01? rev. 1.00 49 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu register lvr&power on wdt overfow (normal mode) wdt overfow ( halt mode ) tkt ? r 0000 0000 0000 0000 u uuu uuuu tkc0 -000 0000 -000 0000 -uuu uuuu tk16dl 0000 0000 0000 0000 u uuu uuuu tk16dh 0000 0000 0000 0000 u uuu uuuu tkc1 ---- --11 ---- --11 ---- --uu tk ? 016dl 0000 0000 0000 0000 u uuu uuuu tk ? 016dh 0000 0000 0000 0000 u uuu uuuu tk ? 0rol 0000 0000 0000 0000 u uuu uuuu tk ? 0roh ---- --00 ---- --00 ---- --uu tk ? 0c0 0000 0000 0000 0000 u uuu uuuu tk ? 0c1 0-00 0000 0-00 0000 u -uu uuuu tk ? 116dl 0000 0000 0000 0000 u uuu uuuu tk ? 116dh 0000 0000 0000 0000 u uuu uuuu tk ? 1rol 0000 0000 0000 0000 u uuu uuuu tk ? 1roh ---- --00 ---- --00 ---- --uu tk ? 1c0 0000 0000 0000 0000 u uuu uuuu tk ? 1c1 0000 0000 0000 0000 u uuu uuuu eec ---- 0000 ---- 0000 ---- uuuu note: - not implement u stands for unchanged x stands for unknown rev. 1.00 50 ? a ? 0 ?? ? 01 ? rev. 1.00 51 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu bs84c12a-3 register register lvr&power on wdt overfow (normal mode) wdt overfow ( halt mode ) iar0 ---- ---- ---- ---- ---- ---- ? p0 xxxx xxxx xxxx xxxx uuuu uuuu iar1 ---- ---- ---- ---- ---- ---- ? p1 xxxx xxxx xxxx xxxx uuuu uuuu bp ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu tbhp ---x xxxx ---u uuuu ---u uuuu status --00 xxxx --1u uuuu --11 uuuu s ? od 0000 0011 0000 0011 uuuu uuuu ctrl 0-00 -x00 0-00 -x00 u-uu -uuu integ ---- --00 ---- --00 ---- --uu intc0 -000 0000 -000 0000 -uuu uuuu intc1 -000 -000 -000 -000 -uuu -uuu lvrc 0000 0000 0000 0000 u uuu uuuu pa 1--1 1111 1--1 1111 u--u uuuu pac 1--1 1111 1--1 1111 u--u uuuu papu 0--0 0000 0--0 0000 u--u uuuu pawu 0--0 0000 0--0 0000 u--u uuuu wdtc 0101 0011 0101 0011 uuuu uuuu tbc --00 ---- --00 ---- --uu ---- t ? r 0000 0000 0000 0000 uuuu uuuu t ? rc --00 -000 --00 -000 --uu -uuu eea --11 1111 --11 1111 --uu uuuu eed 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 u uuu uuuu pbc 1111 1111 1111 1111 u uuu uuuu pbpu 0000 0000 0000 0000 u uuu uuuu i ? ctoc 0000 0000 0000 0000 uuuu uuuu si ? c0 0000 -00- 0000 -00- uuuu Cuu- si ? c1 1000 0001 1000 0001 uuuu -uuu si ? d 0000 0000 0000 0000 uuuu uuuu si ? c ? --11 1111 --11 1111 --uu uuuu si ? a 0000 0000 0000 0000 u uuu uuuu adrl(adrfs=0) xxxx ---- xxxx ---- uuuu ---- adrl(adrfs=1) xxxx xxxx xxxx xxxx uuuu uuuu adrh(adrfs=0) xxxx xxxx xxxx xxxx uuuu uuuu adrh(adrfs=1) ---- xxxx ---- xxxx ---- uuuu adcr0 0110 0000 0110 0000 uuuu uuuu adcr1 00-0 -000 00-0 -000 uu-u -uuu acerl 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 u uuu uuuu pdc 1111 1111 1111 1111 u uuu uuuu pdpu 0000 0000 0000 0000 u uuu uuuu rev. 1.00 50 ?a? 0?? ?01? rev. 1.00 51 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu register lvr&power on wdt overfow (normal mode) wdt overfow ( halt mode ) pc 1111 1111 1111 1111 u uuu uuuu pcc 1111 1111 1111 1111 u uuu uuuu pcpu 0000 0000 0000 0000 u uuu uuuu tkt ? r 0000 0000 0000 0000 u uuu uuuu tkc0 -000 0000 -000 0000 -uuu uuuu tk16dl 0000 0000 0000 0000 u uuu uuuu tk16dh 0000 0000 0000 0000 u uuu uuuu tkc1 ---- --11 ---- --11 ---- --uu tk ? 016dl 0000 0000 0000 0000 u uuu uuuu tk ? 016dh 0000 0000 0000 0000 u uuu uuuu tk ? 0rol 0000 0000 0000 0000 u uuu uuuu tk ? 0roh ---- --00 ---- --00 ---- --uu tk ? 0c0 0000 0000 0000 0000 u uuu uuuu tk ? 0c1 0-00 0000 0-00 0000 u -uu uuuu tk ? 116dl 0000 0000 0000 0000 u uuu uuuu tk ? 116dh 0000 0000 0000 0000 u uuu uuuu tk ? 1rol 0000 0000 0000 0000 u uuu uuuu tk ? 1roh ---- --00 ---- --00 ---- --uu tk ? 1c0 0000 0000 0000 0000 u uuu uuuu tk ? 1c1 0000 0000 0000 0000 u uuu uuuu tk ?? 16dl 0000 0000 0000 0000 uuuu uuuu tk ?? 16dh 0000 0000 0000 0000 uuuu uuuu tk ?? rol 0000 0000 0000 0000 uuuu uuuu tk ?? roh ---- --00 ---- --00 ---- --uu tk ?? c0 0000 0000 0000 0000 uuuu uuuu tk ?? c1 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- uuuu note: - not implement u stands for unchanged x stands for unknown rev. 1.00 5 ? ? a ? 0 ?? ? 01 ? rev. 1.00 5? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a ~ pd. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list BS84B08A-3 register name bit 7 6 5 4 3 2 1 0 pawu d7 d4 d ? d ? d1 d0 papu d7 d4 d ? d ? d1 d0 pa d7 d4 d ? d ? d1 d0 pac d7 d4 d ? d ? d1 d0 pbpu d7 d6 d5 d4 d ? d ? d1 d0 pb d7 d6 d5 d4 d ? d ? d1 d0 pbc d7 d6 d5 d4 d ? d ? d1 d0 pdpu d7 d6 d5 d4 d ? d ? d1 d0 pd d7 d6 d5 d4 d ? d ? d1 d0 pdc d7 d6 d5 d4 d ? d ? d1 d0 bs84c12a-3 register name bit 7 6 5 4 3 2 1 0 pawu d7 d4 d ? d ? d1 d0 papu d7 d4 d ? d ? d1 d0 pa d7 d4 d ? d ? d1 d0 pac d7 d4 d ? d ? d1 d0 pbpu d7 d6 d5 d4 d ? d ? d1 d0 pb d7 d6 d5 d4 d ? d ? d1 d0 pbc d7 d6 d5 d4 d ? d ? d1 d0 pcpu d ? d ? d1 d0 pc d ? d ? d1 d0 pcc d ? d ? d1 d0 pdpu d7 d6 d5 d4 d ? d ? d1 d0 pd d7 d6 d5 d4 d ? d ? d1 d0 pdc d7 d6 d5 d4 d ? d ? d1 d0 rev. 1.00 5? ?a? 0?? ?01? rev. 1.00 5 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high re sistors a re se lected usi ng re gisters p apu~pdpu, a nd a re i mplemented usi ng we ak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 i/o port a bit 7 pull-high control 0: disable 1: enable b it 6 ~ 5 unimplemented, read as 0 b it 4 ~ 0 i/o port a bit 4 ~ bit 0 pull-high control 0: disable 1: enable pbpu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 i/o port b bit 7 ~ bit 0 pull-high control 0: disable 1: enable pcpu register C bs84c12a-3 bit 7 6 5 4 3 2 1 0 name d ? d ? d1 d0 r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 4 unimplemented, read as 0 b it 3 ~ 0 i/o port c bit 3 ~ bit 0 pull-high control 0: disable 1: enable pdpu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 i/o port d bit 7 ~ bit 0 pull-high control 0: disable 1: enable rev. 1.00 54 ? a ? 0 ?? ? 01 ? rev. 1.00 55 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 i/o port a bit 7 pull-high control 0: disable 1: enable b it 6 ~ 5 unimplemented, read as 0 b it 4 ~ 0 i/o port a bit 4 ~ bit 0 w ake up control 0: disable 1: enable i/o port control registers each i/o port has its ow n control register known as p ac~pdc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 b it 7 i/o port a bit 7 input/output control 0: disable 1: enable b it 6 ~ 5 unimplemented, read as 0 b it 4 ~ 0 i/o port a bit 4 ~ bit 0 input/output control 0: disable 1: enable rev. 1.00 54 ?a? 0?? ?01? rev. 1.00 55 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu pbc register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 b it 7 ~ 0 i/o port b bit 7~ bit 0 input/output control 0: output 1: input pcc register C bs84c12a-3 bit 7 6 5 4 3 2 1 0 name d ? d ? d1 d0 r/w r/w r/w r/w r/w por 1 1 1 1 b it 7 ~ 4 unimplemented, read as 0 b it 3 ~ 0 i/o port c bit 3 ~ bit 0 input/output control 0: disable 1: enable pdc register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 b it 7 ~ 0 i/o port d bit 7 ~ bit 0 input/output control 0: disable 1: enable rev. 1.00 56 ? a ? 0 ?? ? 01 ? rev. 1.00 57 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. ??? ?? ? ? ? generic input/output structure ? ? ? ? ? ? - ? ? ? ? ? ? ? ? - a/d input/output structure rev. 1.00 56 ?a? 0?? ?01? rev. 1.00 57 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pdc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port dat a regi sters, p a~pd, a re frst progra mmed. se lecting whi ch pi ns a re i nputs and whi ch are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming individual b its i n t he p ort c ontrol r egister u sing t he set [ m].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer/event counter the provision of timers form an important part of any microcontroller , giving the designer a means of carrying out time related functions. the devices contain one 8-bit. the 8-bit timer is a general timer. t he p rovision of a n i nternal p rescaler t o t he c lock c ircuitry o n gives a dded ra nge t o t he t imers. there are two types of registers related to the t imer/event counter . the first is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the t imer/event counter. the second type of associated register is the t imer control register which defnes the timer options. ? ? ? ? ? ? ? ? -? ? ? ? ? ? timer/event counter confguring the timer/event counter input clock source the t imer/event count er c lock sourc e c an ori ginate from e ither t he syst em c lock f sys or t he f sub oscillator, the choice of which is determined by the ts bit in the tmrc register . this internal clock source is frst divided by a prescaler , the division ratio of which is conditioned by the t imer control register bits tpsc0~tpsc2. rev. 1.00 58 ? a ? 0 ?? ? 01 ? rev. 1.00 59 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu timer register C tmr the time r register is a special function register located in the special purpose data memory and is the place where the actual timer value is stored, it is known as tmr. the value in the timer register increases by one each time an inter nal clock pulse is received the tim er will count from the initial value loaded by the preload register to the full count of ffh at which point the timer overfows and an internal inte rrupt signal is generated. the timer value will then be reset with the init ial preload register value and continue counting. note that to achie ve a maximum full range count of ffh, the preload register must frst be cleared to all z eros. i t sh ould b e n oted t hat a fter p ower-on, t he p reload r egisters wi ll b e i n a n u nknown condition. note that if the t imer/event counter is in an off condition and data is written to its preload register , this data will be immediately written into the actual counter . however , if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overfow occurs. timer control register C tmrc the t imer control register is known as tmrc. it is the t imer control register together with the corresponding timer register that control the full operation of the t imer/event counter . before the timer can be used, it is essential that the t imer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. the timer -on bit, which is bit 4 of the t imer control register and known as t on, provides the basic on/of f control of the timer . setting the bit high allows the counter to run, clearing the bit stops the counter . bits 0~2 of the t imer control register determine the division ratio of the input clock prescaler. the ts bit selects the internal clock source. tmrc register bit 7 6 5 4 3 2 1 0 name ts ton tpsc ? tpsc1 tpsc0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7 ~ 6 unimplemented, read as 0 bit 5 ts : t imer/event counter clock source 0: f sys 1: f sub bit 4 ton : t imer/event counter counting enable 0: disable 1: enable b it 3 unimplemented, read as 0 bits 2 ~ 0 tpsc2~tpsc0 : t imer prescaler rate selection timer internal clock= 000: f tp 001: f tp /2 010: f tp /4 011: f tp /8 100: f tp /16 101: f tp /32 110: f tp /64 111: f tp /128 rev. 1.00 58 ?a? 0?? ?01? rev. 1.00 59 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu timer operation the t imer/event counter is utili z ed to measure fxed time intervals, providing an internal interrupt signal e ach t ime t he t imer/event count er ove rflows. t he t imer i nput c lock sourc e i s e ither f sys or f sub , however, this timer clock source is further divided by a prescaler , the value of which is determined by the bits tpsc2~tpsc0 in the t imer control register . the timer -on bit, t on must be set high to enable the timer to run. each time an internal clock transition occurs, the timer increments by one; when the timer is full and overfows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. a timer overfow condition and corresponding internal interrupt is one of the wake-up sources, however , the internal i nterrupts c an be disabled by e nsuring t hat t he t imer e nable bi t i n t he i nterrupt re gister i s reset to zero . prescaler bits t psc0~tpsc2 of t he t mrc re gister c an be use d t o de fine a di vision ra tio for t he i nternal clock source of the t imer/event counter enabling longer time out periods to be setup. programming considerations when t he t imer/event c ounter i s r ead, o r i f d ata i s wr itten t o t he p reload r egister, t he c lock i s inhibited to avoid errors, however as this may result in a counting error , this should be taken into account by the programmer. care must be taken to ensure that the timer is properly initialised before using it for the frst time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. it is also important to ensure that an initial value is frst loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialised the timer can be turned on and of f by controlling the enable bit in the timer control regis ter. when the t imer/event counter overf ows, its corres ponding interrupt request flag in the interrupt control register will be set. if the t imer/event counter interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are enabl ed or not, a t imer/event counter overfow will also generate a wake-up signal if the device is in a power-down condition. t o prevent such a wake-up from occurring, the timer interrupt request fag should frst be set high before issuing the halt instruction to enter the idle/sleep mode. rev. 1.00 60 ? a ? 0 ?? ? 01 ? rev. 1.00 61 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. part no. input channels a/d channel select bits input pins bs84b08a- ? 8 acs4 ? acs ? ~acs0 an0~an7 bs84c1 ? a- ? 8 acs4 ? acs ? ~acs0 an0~an7 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. ? ? ?? ? ? ? ?? ? - ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ?? ? a/d converter structure a/d converter register description overall operation of the a /d converter is controlled us ing fve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d ? d ? d1 d0 adrl(adrfs=1) d7 d6 d5 d4 d ? d ? d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs ? acs1 acs0 adcr1 acs4 v 119 en vrefs adck ? adck1 adck0 acerl ace7 ace6 ace5 ace4 ace ? ace ? ace1 ace0 a/d converter register list rev. 1.00 60 ?a? 0?? ?01? rev. 1.00 61 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter , they require two data registers to store the converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow by te re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digiti z ed conversion value. as only 12 bits of the 16-bit register space is utili z ed, the format in w hich the data is s tored is controlled by the a drfs bit in the a dcr0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d ? d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d ? d ? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1, acerl are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter , the digiti z ed data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. t he ac s 2 ~acs0 b its i n t he adc r0 r egister a nd ac s4 b it i s t he adc r1 r egister d efne the adc input channel number . as the device contains only one actual analog to digital converter hardware c ircuit, e ach of t he i ndividual 8 a nalog i nputs m ust b e ro uted t o t he c onverter. it i s t he function o f t he ac s4 a nd ac s2 ~ acs0 b its t o d etermine wh ich a nalog c hannel i nput signals o r internal 1.19v is actually connected to the internal a/d converter. the acerl control register contai ns the ace7~ace0 bits which determine which pins on port d are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corres ponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. rev. 1.00 6 ? ? a ? 0 ?? ? 01 ? rev. 1.00 6? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu adcr0 register bit 7 6 5 4 3 2 1 0 name start eocb adoff adrfs acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 b it 7 start : start the a/d conversion 010 : start 01 : reset the a/d converter and set eocb to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. b it 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. b it 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. b it 4 adrfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. b it 3 unimplemented, read as 0 b it 2 ~ 0 acs2 ~ acs0 : select a/d channel (when acs4 is 0) 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7 these are the a/d channel select control bits. as there is only one internal hardware a/d convert er each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.19v will be routed to the a/d converter. rev. 1.00 6? ?a? 0?? ?01? rev. 1.00 6 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu adcr1 register bit 7 6 5 4 3 2 1 0 name acs4 v119en vrefs adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 acs4 : select internal 1.19v as adc input control 0: disable 1: enable this bit enables 1.19v to be connected to the a/d converter . the v 119 en bit must frst have been set to enable the bandgap circuit 1.19v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.19v voltage will be routed to the a/d converter and the other a/d input channels disconnected. b it 6 v 119 en : internal 1. 19 v control 0: disable 1: enable this bit controls the internal b andgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap 1. 19 v voltage can be used by the a/d converter . if 1. 19 v is not used by the a/d converter and the l vr function is disabled then the bandgap reference circuit will be automatically switched of f to conserve power . when 1.19 v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. b it 5 unimplemented, read as 0 b it 4 vrefs : select adc reference voltage 0: internal adc power 1: v ref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high then the a/d converter reference voltage is supplied on the external v ref pin. if the pin is low then the internal referenc e is used which is taken from the power supply pin vdd. b it 3 unimplemented, read as 0 b it 2 ~ 0 adck2 ~ adck0 : select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned (f sub for test) these three bits are used to select the clock source for the a/d converter. rev. 1.00 64 ? a ? 0 ?? ? 01 ? rev. 1.00 65 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu acerl register bit 7 6 5 4 3 2 1 0 name ace7 ace6 ace5 ace4 ac e ? ac e ? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 b it 7 ace7 : defne p d7 is a/d input or not 0: not a/d input 1: a/d input, an7 b it 6 ace6 : defne p d6 is a/d input or not 0: not a/d input 1: a/d input, an6 b it 5 ace5 : defne p d5 is a/d input or not 0: not a/d input 1: a/d input, an5 b it 4 ace4 : defne p d4 is a/d input or not 0: not a/d input 1: a/d input, an4 b it 3 ace3 : defne p d3 is a/d input or not 0: not a/d input 1: a/d input, an3 b it 2 ace2 : defne p d 2 is a/d input or not 0: not a/d input 1: a/d input, an2 b it 1 ace1 : defne p d 1 is a/d input or not 0: not a/d input 1: a/d input, an1 b it 0 ace0 : defne p d 0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit i n t he adcr0 regi ster i s use d t o i ndicate whe n t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow t o t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. rev. 1.00 64 ?a? 0?? ?01? rev. 1.00 65 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu although the a/ d clock source is determined by the system clock f sys , and by bits adck2~adck0, there a re so me l imitations o n t he m aximum a/ d c lock so urce sp eed t hat c an b e se lected. as t he minimum value of permissible a/d clock period, t adck , is from 0.5s, care must be taken for system c lock fre quencies. for e xample, i f t he syst em c lock ope rates a t a fre quency of 4mhz , t he adck2~adck0 bits should not be set to 000b or 1 10b . doing so will give a/d clock periods that are less than the minimum a/d clock period or greater than the maximum a/d clock period which may result in inaccurate a/d conversion values. refer t o t he fol lowing t able for e xamples, wh ere va lues m arked wi th a n a sterisk * sh ow whe re, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1 ? hz 1s ? s 4s 8s 16s* ?? s* 64s* undefned ?? hz 500ns 1s ? s 4s 8s 16s* ?? s* undefned 4 ? hz ? 50ns* 500ns 1s ? s 4s 8s 16s* undefned 8 ? hz 1 ? 5ns* ? 50ns* 500ns 1s ? s 4s 8s undefned 1 ?? hz 8 ? ns* 167ns* ??? ns* 667ns 1. ?? s ? .67 s 5. ?? s undefned 16 ? hz 6 ? .5ns* 1 ? 5ns* ? 50ns* 500ns 1s ? s 4s undefned ? 0 ? hz 50ns* 100ns* ? 00ns* 400ns* 800ns 1.6s ? . ? s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace7~ace0 bits in the acerl registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of t he a/ d a nalog i nput pi ns a re pi n-shared wi th t he i/ o pi ns on por t a a s we ll a s ot her functions. the ace7~ace0 bits in the acerl registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace7~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way , pins can be changed under program control to change their function bet ween a/ d input s and othe r func tions. al l pull -high resi stors, whi ch are se tup through register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p ac port control register to enable the a/d input as when the ace7~ace0 bits enable an a/d input, the status of the port control register will be overridden. rev. 1.00 66 ? a ? 0 ?? ? 01 ? rev. 1.00 67 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu the a/d converter has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of vref . ? ? ? ? ? ? a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4 , acs2 ~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace7~ace0 bits in the acerl register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade , must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr 0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when t his bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. rev. 1.00 66 ?a? 0?? ?01? rev. 1.00 67 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardw are will begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck where t adck is equal to the a/d clock period. ? ? ? ? ? ?? ? ? - ??- ? ??- ? ? ? ? - ? ? ? ? ? ? ? ? - ? ? ? ? ? ? ? ? ? ?- ? a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as t he de vice c ontain s a 12-bi t a/ d c onverter, i ts ful l-scale c onverted di giti z ed va lue i s e qual t o fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= (v dd or v ref ) / 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) / 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digiti z ed value will change at a point 1.5 lsb below the v dd or v ref level. rev. 1.00 68 ? a ? 0 ?? ? 01 ? rev. 1.00 69 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ? ? ? ? ? ? ?? ? ? ? ideal a/d transfer function a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st example, t he m ethod o f p olling t he e ocb b it i n t he adcr0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1. 19 v clr adoff mov a,0fh ; setup acerl to confgure pins an0~an3 mov acerl,a mov a,0 1 h mov adcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : jmp start_conversion ; start next a/d conversion rev. 1.00 68 ?a? 0?? ?01? rev. 1.00 69 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1. 19 v clr adoff mov a,0fh ; setup acerl to confgure pins an0~an3 mov acerl,a mov a,0 1 h mov adcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti rev. 1.00 70 ? a ? 0 ?? ? 01 ? rev. 1.00 71 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu touch key function each device provides multiple touch key functions. the touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. touch key structure the touch keys are pin shared with the pb and pc logic i/o pins, with the desired function chosen via register b its. ke ys a re o rgani z ed i nto g roups o f f our, wi th e ach g roup k nown a s a m odule a nd having a module number , m0 to m 2 . each module is a fully independent set of four t ouch keys and each t ouch key has its own oscillator . each module contains its own control logic circuits and register set. examination of the register names will reveal the module number it is referring to. device keys - n touch key module touch key shared i/o pin bs84b08a- ? 8 ? 0 k1~k4 pb0~pb ? ? 1 k5~k8 pb4~pb7 bs84c1 ? a- ? 1 ? ? 0 k1~k4 pb0~pb ? ? 1 k5~k8 pb4~pb7 ? ? k9~k1 ? pc0~pc ? touch key register defnition each t ouch k ey m odule, wh ich c ontains f our t ouch k ey f unctions, h as i ts o wn su ite r egisters. t he following table shows the register set for each touch key module. the mn within the register name refers to the t ouch key module number , BS84B08A-3 has a range of m0 to m1, bs84c12a-3 has a range of m0 to m2. name usage tkt ? r touch ke ? 8-bit timer/counter register tkc0 counter on-off and clear control/reference clock control/start bit tk16dl touch ke ? module 16-bit counter low b ? te contents tk16dh touch ke ? module 16-bit counter high b ? te contents tkc1 touch ke ? osc frequenc ? select tk ? n16d l ? odule n 16-bit counter low b ? te contents tk ? n16d h ? odule n 16-bit counter high b ? te contents tk ? nrol reference osc internal capacitor select tk ? nroh reference osc internal capacitor select tk ? nc0 control register 0 ? ultiplexer ke ? select tk ? nc1 control register 1 ke ? oscillator control/reference oscillator control/ touch ke ? or i/o select register listing rev. 1.00 70 ?a? 0?? ?01? rev. 1.00 71 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu register name bit 7 6 5 4 3 2 1 0 tkt ? r d7 d6 d5 d4 d ? d ? d1 d0 tkc0 tkrcov tkst tkcfov tk16ov tscs tk16s1 tk16s0 tk16dl d7 d6 d5 d4 d ? d ? d1 d0 tk16dh d7 d6 d5 d4 d ? d ? d1 d0 tkc1 tkfs1 tkfs0 tk- ? n16dl d7 d6 d5 d4 d ? d ? d1 d0 tk- ? n16dh d7 d6 d5 d4 d ? d ? d1 d0 tk ?n- n- rol d7 d6 d5 d4 d ? d ? d1 d0 tk ?n- n- roh d9 d8 tk ? nc0 ? n ? xs1 ? n ? xs0 ? ndfen ? nfilen ? nsofc ? n sof ? ? nsof1 ? nsof0 tk ? nc1 ? ntss ? nroen ? nkoen ? nk4io ? n k ? io ? n k ? io ? nk1io touch key module (n=0~2) tktmr register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~0 touch key 8-bit timer/counter register time slot counter overfow set-up time is (256-tktmr[7:0]) x 32 rev. 1.00 7 ? ? a ? 0 ?? ? 01 ? rev. 1.00 7? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu tkc0 register bit 7 6 5 4 3 2 1 0 name tkrcov tkst tkcfov tk16ov tscs tk16s1 tk16s0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 tkrcov : t ime slot counter overfow fag 0: no overfow 1: overfow if module 0 or all module (select by tscs bit) time slot counter is overfow , the t ouch key interrupt request fag will be set (tkmf) and all module key osc and ref osc auto st op. al l m odule 16 -bit c /f c ounter, 16 -bit c ounter, 5- bit t ime sl ot c ounter a nd 8-bit time slot timer counter will be automatically switched off. bit 5 tkst : start t ouch key detection control bit 0: stopped 01: started in all modules the16-bit c/f counter , 16-bit counter , 5-bit time slot counter will be a utomatically c leared whe n t his bi t i s c leared t o 0 (8-bi t progra mmable t ime slot counter will not be cleared, which overflow time is setup by user). when this bit changes from low to high, the 16-bit c/f counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically on and enable key osc and ref osc output clock input these counter. bit 4 tkcfov : t ouch key module 16-bit c/f counter overfow fag 0: not overfow 1: overfow this bit must be cleared by software. bit 3 tk16ov : t ouch key module 16-bit counter overfow fag 0: not overfow 1: overfow this bit must be cleared by software. bit 2 tscs : t ouch key time slot counter select 0: each module use own time slot counter. 1: all t ouch key module use module 0 time slot counter. bit 1~0 tk16s1~ tk16s0 : the touch key module 16-bit counter clock source select 00: f sys 01: f sys /2 10: f sys /4 11: f sys /8 tkc1 register bit 7 6 5 4 3 2 1 0 name tkfs1 tkfs0 r/w r/w r/w por 0 0 b it 7 ~2 unimplemented, read as 0 bit 1~0 tkfs1~tkfs0 : t ouch key osc frequency select 00: 500khz 01: 1000 khz 10: 1500 khz 11: 2000 khz rev. 1.00 7? ?a? 0?? ?01? rev. 1.00 7 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu tk16dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 touch key module 16-bit counter low byte contents tk16dh register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 touch key module 16-bit counter high byte contents tkmn16dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 module n 16-bit counter low byte contents tkmn16dh register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~0 module n 16-bit counter high byte contents tkmnrol register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~0 reference osc internal capacitor select osc internal capacitor select : (tkmn ro[9:0] x 50pf ) / 1024 tkmnroh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7 ~2 unimplemented, read as 0 bit 1~0 reference osc internal capacitor select osc internal capacitor select : (tkmnro[9:0] x 50pf) / 1024 rev. 1.00 74 ? a ? 0 ?? ? 01 ? rev. 1.00 75 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu tkmnc0 register bit 7 6 5 4 3 2 1 0 name ? n ? xs1 ? n ? xs0 ? ndfen ? nfilen ? nsofc ? n sof ? ? nsof1 ? nsof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~6 mnmxs1~mnmxs0: multiplexer k ey select b it 5 mndfen : multi-frequency control 0: disable 1: enable b it 4 mnfilen : filter function control 0: disable 1: enable bit3 mnsofc : c to f osc frequency hopping function control 0: the frequency hopping function is controlled by mnsof2~ mnsof0 bits 1: the frequency hopping function is controlled by hardware regardless of what is the state of mnsof2~ mnsof0 bits bit 2~0 mnsof2~ mnsof0 : selecting key osc and ref osc frequency as c to f osc is controlled by software 000: 1380khz 001: 1500khz 010: 1670khz 011: 1830khz 100: 2000khz 101: 2230khz 110: 2460khz 111 : 2740khz the frequency which is mentioned here will be changed when the external or internal capacitor is with dif ferent value. if the touch key operates at 2mhz frequency , users can adjust the frequency in scale when select other frequency. bit module number mnmxs1 mnmxs0 m0 m1 m2 0 0 ke ? 1 ke ? 5 ke ? 9 0 1 ke ? ? ke ? 6 ke ? 1 0 1 0 ke ? ? ke ? 7 ke ? 11 1 1 ke ? 4 ke ? 8 ke ? 1 ? rev. 1.00 74 ?a? 0?? ?01? rev. 1.00 75 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu tkmnc1 register bit 7 6 5 4 3 2 1 0 name ? ntss ? nroen ? nkoen ? nk4io ? nk ? io ? nk ? io ? nk1io r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 mntss : t ime slot counter clock select 0:reference osc 1:f sys /4 b it 6 unimplemented, read as 0 bit 5 mnroen : reference osc control 0: disable 1: enable bit 4 mnkoen : key osc control 0: disable 1: enable bit 3~0 mnk4io~ mnk1io : i/o pin or touch key function select mnk4oen m0 m1 m2 pb3/key4 pb7/key8 pc3/key12 0 i/o 1 touch ke ? input mnk3oen m0 m1 m2 pb2/key3 pb6/key7 pc2/key11 0 i/o 1 touch ke ? input mnk2oen m0 m1 m2 pb1/key2 pb5/key6 pc1/key10 0 i/o 1 touch ke ? input mnk1oen m0 m1 m2 pb0/key1 pb4/key5 pc0/key9 0 i/o 1 touch ke ? input rev. 1.00 76 ? a ? 0 ?? ? 01 ? rev. 1.00 77 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu touch key operation when a fnger t ouches or i s i n proxi mity t o a t ouch pa d, t he c apacitance of t he pa d wi ll i ncrease. by using this capa citance variation to change slightly the frequency of the internal sense oscillator , touch actions can be sensed by mea suring these frequency changes. using an internal programmable divider the reference clock is used to generate a fixed time period. by counting a number of generated clock cycles from the sense oscillator during this fxed time period touch key actions can be determined. during this reference clock fixed interval, the number of clock cycles generated by the s ense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. these device s contain four touch key inputs which are shared with logical i/o pins, with the desired function selected using register bits. using the tscs bit in the tkc0 register can select the module 0 time slot counter as the time slot counter for a ll m odules. al l m odules use t he sa me st arted si gnal. t he 16-bit c/ f c ounter, 16- bit counter, 5-bit time slot counter in all module s will be automatically cleared when this bit is cleared to "0" , but the 8-bit programmable time slot counter will not be cleared. the overfow time is setup by user . when this bit changes from low to high , the 16-bit c/f counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched on. the key oscillator and reference oscillator in all modules will be automatically stopped and the 16-bit c/f counte r, 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched of f when the 5-bit time slot counter overfows. the clock source for the time slot c ounter and 8+5 bi t count er, i s sourc ed from t he refe rence osc illator or f sys /4. the refe rence oscillator and key oscillator will be enabled by setting the mnroen bit and mnkoen bits in the tkmnc1 register . w hen the time s lot counter in all the touch key modules or in the touch key module 0 overfow s, a n actual t ouch k ey interrupt will take place . the touch keys mentioned here are the keys which are enabled. each touch key module, which consists of four touch keys , key 1~key 4 is contained in module 0, key 5~key 8 is contained in module 1 and key 9~key 12 is contained in module 2. each touch key module has an identical structure. rev. 1.00 76 ?a? 0?? ?01? rev. 1.00 77 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu key 1 key 2 key 3 key 4 key osc key osc key osc key osc mux . filter overflow 16 -bit counter overflow f sys ,f sys /2, f sys / 4,f sys / 8 tk 16s1~ tk 16s 0 5- bit time slot counter overflow 8- bit time slot timer counter ref osc mux . f sys / 4 mntss 8- bit time slot timer counter preload register overflow multi - frequency 16- bit c / f counter note: each touch key module contains the content in the dash line. touch key module block diagram rev. 1.00 78 ? a ? 0 ?? ? 01 ? rev. 1.00 79 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu the touch key sense oscillator and reference oscillator timing diagram is shown in the following fgure: ?? ?? ?? ?? tkst key osc en ref osc en key osc clk fr ef enck time slot counter overflow flag set touch key interrupt request flag tstmr overflow * 32 ftmck (dfen=0) ftmck (dfen=1) hardware set to ?0? touch key or i/o function select touch key interrupt the touch key only has single inter rupt, when the time slot counter in all the touch key modules or in the touch key module 0 overfows, an actual touch key interrupt will take place. the touch keys mentioned h ere a re t he k eys wh ich a re e nabled. t he16-bit c /f c ounter, 1 6-bit c ounter, 5 -bit t ime sl ot counter and 8-bit time slot counter in all modules will be automatically cleared. the tkcfov flag, which is the 16-bit c/f counter overflow flag will go high when a ny of the touch k ey m odule 16-bit c /f counter overf ow s. as this f ag w ill not be automatically cleared, it has to be cleared by the application program. the m odule 0 o nly contains one 1 6-bit c ounter . the t k16ov f lag, wh ich i s t he 16-bit c ounter overfow fag will go high when the 16-bit counter overfow s. as this fag will not be automatically cleared, it has to be cleared by the application program. more details regarding the touch key interrupt is located in the interrupt section of the datasheet. rev. 1.00 78 ?a? 0?? ?01? rev. 1.00 79 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu programming considerations after t he rel evant regi sters are se tup, t he t ouch key det ection process i s i nitiated t he cha nging t he tk st bit from low to high. this will enable and synchronise all relevant oscillators. the tkrcov fag, whi ch i s t he t ime sl ot c ounter fa g wi ll go hi gh a nd re main hi gh unt il t he c ounter ove rfows. when this happens an interrupt signal will be generated. when the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency. serial interface module C sim these devices contain a serial interface module, which include both the four line spi interface and the two line i2c interface types, to allow an easy method of communic ation with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i2c based hardware such as sensors, flash memory or eeprom memory , etc. the sim interface pins are pin-shared with other i/o pins and must be selected using the simen bit in the simc0 register . as both interface types share the same pins and registers, the choice of whether the spi or i2c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a single master , but this device provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must frst be enabled by setting the correct bits in the simc0 and simc2 registers. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations b eing i mplemented by t he m aster. t he ma ster a lso c ontrols t he c lock si gnal. as t he d evice only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable scs pin function, set csen bit to " 0 " the scs pin will be as i/o function. spi master/slave connection rev. 1.00 80 ? a ? 0 ?? ? 01 ? rev. 1.00 81 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ?? ? ? ?? ? ? ?- ? ? ? ? ? ? ? ? spi block diagram the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 si ? c0 si ?? si ? 1 si ? 0 si ? en si ? d d7 d6 d5 d4 d ? d ? d1 d0 si ? c ? ckpolb ckeg ? ls csen wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. rev. 1.00 80 ?a? 0?? ?01? rev. 1.00 81 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function a nd t o se t t he da ta t ransmission c lock fre quency. al though not c onnected wi th t he spi function, the simc0 register is also used to control the peripheral clock prescaler . register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc. simc0 register bit 7 6 5 4 3 2 1 0 name si ?? si ? 1 si ? 0 si ? en r/w r/w r/w r/w r/w por 1 1 1 0 b it 7 ~ 5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is timer overfow frequency/2 101: spi slave mode 110: i 2 c mode 111: reserved these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e select ion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the t imer/event counter . if the spi slave mode is selected then the clock will be supplied by an external master device. b it 4~2 unimplemented, read as 0 b it 1 simen : sim control 0: disable 1: enable the bi t is the overall on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be as i/o functi on and the sim operating current will be reduced to a minimum value. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of t he i 2 c c ontrol bi ts such a s ht x a nd t xak wi ll rem ain a t t he pre vious settings and should therefore be frst initialised by the application program while the relevant i 2 c flags s uch as h cf, h aas, h bb, s rw and rx ak w ill be s et to their default states. b it 0 unimplemented, read as 0 rev. 1.00 8 ? ? a ? 0 ?? ? 01 ? rev. 1.00 8? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu simc2 register bit 7 6 5 4 3 2 1 0 name ckpolb ckeg ? ls csen wcol trf r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as 0 bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bi t det ermines the base condit ion of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inactive. when the ckpolb bit is low , then the sck line will be high when the clock is inactive. bit 3 mls : spi data shift order this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable /disable for the scs pin. if this bit is low , then the scs pin will be disabled and placed into a foating condition. if the bit is high the scs pin will be enabled and used as a select pin. bit 1 wcol : spi w rite collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 trf : spi t ransmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the t ransmit/receive complete fag and is set 1 automatically when an spi data transmission is complet ed, but must set to 0 by the application program. it can be used to generate an interrupt. rev. 1.00 8? ?a? 0?? ?01? rev. 1.00 8 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu spi communication after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register , transmission/reception will begin simultaneously . when the data t ransfer is c omplete, t he t rf fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register . the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode. ? ? ? ? ? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ? ? ? spi master mode timing ? ? ? ? ??? ? - ? ? ?? spi slave mode timing C ckeg=0 rev. 1.00 84 ? a ? 0 ?? ? 01 ? rev. 1.00 85 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ? ? ?? ? ? ? ? ? ? ?? ?? ? - ? ?? ?? ? ? ?? ? ? ? ? ? ? ? ?? ?? ?? ? ? ? ? ?? ? ?? ? ?? ? ? ? ? ? ? ? ? spi slave mode timing C ckeg=1 ? ? ? ? ? ? ? ? ? ? ? -? ?? ? ? ? ? ? ? ???? ??? ? ????? ?? ?? ? ???? ? spi transfer control flowchart rev. 1.00 84 ?a? 0?? ?01? rev. 1.00 85 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master /slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, i t i s t he m aster de vice t hat ha s ove rall c ontrol of t he bus. for t h is de vice, wh ich onl y operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. the debounce tim e of the i 2 c interf ace uses the system clock to in ef fect add a debounce time to the external c lock t o re duce t he possi bility of gl itches on t he c lock l ine c ausing e rroneous ope ration. the debounce tim e, is 2 system clocks. t o achieve the required i 2 c data transfer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce tim e. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) ? s ? stem clock debounce f sys > 4 ? hz f sys > 10 ? hz i 2 c minimum f sys frequency rev. 1.00 86 ? a ? 0 ?? ? 01 ? rev. 1.00 87 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu i 2 c registers there are four control registers associated with the i 2 c bus, simc0, simc1 , sima and i2ct oc and one data register , simd. the simd register , which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the micro controller can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register . the sim pins are pin shared with other i/o pins and must be selected using the simen bit in the simc0 register . note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 si ? c0 si ?? si ? 1 si ? 0 si ? en si ? c 1 hcf haas hbb htx txak srw rnic rxak si ? d d7 d6 d5 d4 d ? d ? d1 d0 si ? a a6 a5 iic i ? ctoc ip enabled b ? sa 4 a ? a ? a1 a0 i ? ctoc i ? ctoen i ? ctof i ? ctos5 i ? ctos4 i ? ctos ? i ? ctos ? i ? ctos1 i ? ctos0 i 2 c registers list simc0 register bit 7 6 5 4 3 2 1 0 name si ?? si ? 1 si ? 0 si ? en r/w r/w r/w r/w r/w por 1 1 1 0 bit 7 ~ 5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is timer overfow frequency/2 101: spi slave mode 110: i 2 c mode 111: reserved these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e select ion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the t imer/event counter . if the spi slave mode is selected then the clock will be supplied by an external master device. b it 4~2 unimplemented, read as 0 rev. 1.00 86 ?a? 0?? ?01? rev. 1.00 87 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu bit 1 simen : sim control 0: disable 1: enable the bi t is the overal l on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be as i/o functi on and the sim operating current will be reduced to a minimum value. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of t he i 2 c c ontrol bi ts such a s ht x a nd t xak wi ll rem ain a t t he pre vious settings and should therefore be frst initialised by the application program while the relevant i 2 c flags s uch as h cf, h aas, h bb, s rw and rx ak w ill be s et to their default states. b it 0 unimplemented, read as 0 simc1 register bit 7 6 5 4 3 2 1 0 name hcf haas hbb htx txak srw rnic rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus address match fag 0: not address match 1: address match the hass fag i s t he a ddress m atch fag. t his fag i s used t o de termine i f t he sla ve device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. rev. 1.00 88 ? a ? 0 ?? ? 01 ? rev. 1.00 89 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesti ng to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 rnic : i 2 c running using internal clock control 0: i 2 c running using internal clock 1: i 2 c running not using internal clock the i 2 c module can run w ithout us ing internal clock, and generate an interrupt if the sim interrupt is enabled, which can be used in sleep mode, idle mode, normal(slow) mode. if this bit is set to 1 and mcu is in hal t, slave- receiver can work well but slave-transmitter doesnt work since it needs system clock . bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag the r xak f lag i s t he re ceiver a cknowledge f lag. w hen t he r xak fl ag i s 0, i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determin e if the master receiver wishes to receive the next byte. t he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. i2ctoc register bit 7 6 5 4 3 2 1 0 name i ? ctoen i ? ctof i ? ctos5 i ? ctos4 i ? ctos ? i ? ctos ? i ? ctos1 i ? ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 i2ctoen : i2c t ime-out control 0: disable 1: enable bit 6 i2ctof : t ime-out fag 0: no time-out 1: time-out occurred bit 5~0 i2ctos5~i2ctos0 : t ime-out defnition i 2 c time-out clock source is f sub /32. i 2 c time-out time is given by: ([i2ctos5 : i2ctos0]+1) x (32/f sub ) the simd register is used to store the data being transmitted and received. the same register is used by bot h t he spi a nd i 2 c fun ctions. be fore t he de vice wr ites da ta t o t he i 2 c bus, t he a ctual da ta t o be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the device can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. rev. 1.00 88 ?a? 0?? ?01? rev. 1.00 89 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown sima register bit 7 6 5 4 3 2 1 0 name a6 a5 a4 a ? a ? a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x unknown bit 7~1 a6~a0 : i 2 c slave address a6~ a0 is the i 2 c slave address bit 6 ~ bit 0. the si ma r egister i s a lso u sed b y t he spi i nterface b ut h as t he n ame si mc2. t he sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~ 1 of the sima register define the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 unimplemented, read as 0 ? ? ? ? ? ?-? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? i 2 c block diagram rev. 1.00 90 ? a ? 0 ?? ? 01 ? rev. 1.00 91 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the comple tion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/writ e bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must init ialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and simen bits in the simc0 register to 1 to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sime interrupt enable bit of the interrupt control register to enable the sim interrupt . ? ? ? ? ? ? ? - ?? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart rev. 1.00 90 ?a? 0?? ?01? rev. 1.00 91 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu i 2 c bus start signal the st art signal can only be generated by the master device connec ted to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, t he haas bi t shoul d be e xamined t o se e whe ther t he i nterrupt sourc e ha s c ome from a matching slave address or from the completion of a data byte transfer . when a slave address is matched, the device must be placed in either the transmit mode and then w rite data to the s imd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the sr w bit in the simc1 registe r defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1. if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0. rev. 1.00 9 ? ? a ? 0 ?? ? 01 ? rev. 1.00 9? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. t he o rder o f se rial b it t ransmission i s t he msb fr st a nd t he l sb l ast. after receipt of 8-bits of data, the receiver must transmit an acknowle dge signal, level 0, before it can receive the next data byte. if the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register . if setup as a receive r, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. ? ? ? ? ? ? ? ? - ? - ? ? i 2 c communication timing diagram note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. rev. 1.00 9? ?a? 0?? ?01? rev. 1.00 9 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ? ? ? ? i 2 c bus isr flow chart i 2 c time-out control in order to reduce the problem of i 2 c lockup due to reception of erroneous clock sources, clock, a time-out function is provided. if the clock source to the i 2 c is not received then after a fxed time period, the i 2 c circuitry and registers will be reset. the t ime-out c ounter st arts c ounting on a n i 2 c bus start & address m atch c ondition, a nd is cleared b y a n sc l f alling e dge. b efore t he n ext sc l f alling e dge a rrives, i f t he t ime e lapsed i s greater than the time-out setup by the i2ct oc regis ter, then a time-out condition w ill occur . the time-out function will stop when an i 2 c stop condition occurs. when an i 2 c time -out counte r overfow occurs, the counter will stop and the i2ct oen bit will be cleared to zero and the i2ct o f bit will be set high to indicate that a time-out condition as occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrupt vector . when an i 2 c time-out occurs , the i 2 c i nternal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out si ? d ? si ? a ? si ? c0 no change si ? c1 reset to por condition i 2 c registers after time-out the i2ct of f ag can be cleared by the application program. there are 64 time-out periods w hich can be selected using bits in the i2ctoc register. the time-out time is given by the formula: ((1~64) 32) / f sub . this gives a range of about 1ms to 64ms. note also that the lirc oscillator is continuously enabled . rev. 1.00 94 ? a ? 0 ?? ? 01 ? rev. 1.00 95 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t ouch action or t imer/event counter overfow requires microcontroller attention, their corres ponding interrupt w ill enforce a temporary s uspension of the main program allowing the microcontroller to direct attention to their respective needs. the device s contain several external interrupt and internal interr upts functions. the external interru pt is generated by the action of the external int pin, while the internal interrupts are generated by various internal functions such as the t ouch keys, t imer/event counter, t ime base, sim etc. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc 1 registers which setup the primary interrupts, the second is the integ registers to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global e ? i int pin inte intf touch ke ? ? odule tk ? e tk ? f timer/event counter te tf si ? si ? e si ? f time base tbe tbf eepro ? dee def a/d converter interrupt ade adf interrupt register bit naming conventions interrupt register contents name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ ints1 ints0 intc0 tf tk ? f intf te tk ? e inte e ? i intc1 adf def tbf si ? f ade dee tbe si ? e integ register bit 7 6 5 4 3 2 1 0 name ints1 ints0 r/w r/w r/w por 0 0 b it 7 ~ 2 unimplemented, read as 0 b it 1 ~ 0 ints1, ints0 : defnes int interrupt active edge 00: disabled interrupt 01: rising edge interrupt 10: falling edge interrupt 11: dual edge interrupt rev. 1.00 94 ?a? 0?? ?01? rev. 1.00 95 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu intc0 register bit 7 6 5 4 3 2 1 0 name tf tk ? f intf te tk ? e inte e ? i r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimple mented, read as 0 bit 6 tf : t imer/event counter interrupt request fag 0: no request 1: interrupt request bit 5 tkmf : t ouch key module interrupt request fag 0: no request 1: interrupt request bit 4 intf : int pin interrupt request fag 0: no request 1: interrupt request bit 3 te : t imer/event counter interrupt control 0: disable 1: enable bit 2 tkme : t ouch key module interrupt control 0: disable 1: enable bit 1 inte : int pin interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable intc1 register bit 7 6 5 4 3 2 1 0 name adf def tbf si ? f ade dee tbe si ? e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 6 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 5 tbf : t ime base interrupt request fag 0: no request 1: interrupt request bit 4 simf :sim interrupt request fag 0: no request 1: interrupt request bit 3 ade : a/d converter interrupt control 0: disable 1: enable bit 2 dee : data eeprom control 0: disable 1: enable bit 1 tbe : t ime base interrupt control 0: disable 1: enable bit 0 sime : sim interrupt control 0: disable 1: enable rev. 1.00 96 ? a ? 0 ?? ? 01 ? rev. 1.00 97 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu interrupt operation when the conditions for an interrupt event occur , s uch as a t ouch k ey counter overf ow, t imer/ event counter overfow , etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter addres s from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. all o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. external touch ke? ?odule intf tk?f inte tk?e e?i 04 h e?i 08 h 10 h si? si?f si?e e?i 18 h eepro? def dee e?i interrupt name request flags enable bits ?aster enable vector e?i auto disabled in isr low priorit? high xxe enable bits xxf request flag ? auto reset in isr legend xxf request flag ? no auto reset in isr 0c h 14 h tbf tbe e?i timer / event counter tf te e?i time base 1ch a/ dconverter adf ade e?i interrupt structure rev. 1.00 96 ?a? 0?? ?01? rev. 1.00 97 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu external interrupt the e xternal i nterrupt is c ontrolled by si gnal t ransitions on t he pi n int . an e xternal i nterrupt request will take place when the external interrupt request flag, intf , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, inte, must frst be set. additionally the correc t i nterrupt edge t ype must be se lected usi ng t he int eg regi ster t o ena ble t he ext ernal interrupt function and to choose the trigger edge type. as the external interrupt pin is pin-shared with i/o pin, its can only be confgured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fag, intf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. time base interrupt the function of the t ime base interrupt is to provide regular time signal in the form of an internal interrupt. it is controlled by the overflow signal from its timer function. when th is happens its interrupt request flags tbf will be set. t o allow the program to branch to its interrupt vector address, the global interrupt enable bit, emi and t ime base enable bit, tbe, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfows, a subroutine call to its vector location will take place. when the interrupt is serviced, the interrupt request fag, tbf , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. its clock source originate from the internal clock source f sys or f sub . this f tp input clock passes through a di vider, t he di vision ra tio of whi ch i s se lected by progra mming t he a ppropriate bi ts i n t he t bc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tp , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. rev. 1.00 98 ? a ? 0 ?? ? 01 ? rev. 1.00 99 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu tbc register bit 7 6 5 4 3 2 1 0 name tb1 tb0 r/w r/w r/w por 0 0 b it 7 ~6 unimplemented, read as 0 b it 5~4 tb1 ~ tb0 : select t ime base t ime-out period 00: 1024/f tp 01: 2048/f tp 10: 4096/f tp 11: 8192/f tp b it 3~ 0 unimplemented, read as 0 time base structure timer/event counter interrupt for a t imer/event counter interrupt to occur , the global interrupt enable bit, em i, and the corresponding timer interrupt enable bit, te, must first be set. an actual t imer/event counter interrupt will take place when the t imer/event counter request fag, tf , is set, a situation that will occur when the relevant t imer/event counter overfows. when the interrupt is enabled, the stack is not ful l and a t imer/event counte r n overfl ow oc curs, a subrouti ne c all t o t he relevant t imer interrupt vector , will take place. when the interrupt is serviced, the timer interrupt request fag, tf , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. eeprom interrupt an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or, will take place. when the eeprom interrupt is serviced, the def fag will be automatically cleared and the emi bit will be automatically cleared to disable other interrupts. rev. 1.00 98 ?a? 0?? ?01? rev. 1.00 99 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu touch key interrupt for a t ouch key interrupt to occur , the global interrupt enable bit, emi, and the corresponding touch key interru pt enable tkme must be frst set. an actual t ouch key interrupt will take place when the touch key request fag. tkmf , is set, a situation that will occur when the time slot counter overfows. when the interrupt is enabled, the stack is not full and the touch key time slot counter overfow occurs, a subroutine call to the relevant timer interrupt vector , will take place. when the interrupt is serviced, the t ouch key interrupt request fag, tkmf , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. the tkcfov flag, which is the 16-bit c/f counter overflow flag will go high when a ny of the touch k ey m odule 16-bit c/f counter overf ow s. as this f ag w ill not be automatically cleared, it has to be cleared by the application program. module 0 o nly contains one 16-bit counter . the tk16ov fag, which is the 16-bit counter overfow fag will go high when the 16-bit counter overfow s. as this fag will not be automatically cleared, it has to be cleared by the application program. sim interrupt a sim in terrupt re quest wi ll t ake pl ace whe n t he sim in terrupt re quest fa g, simf , i s se t, whi ch occurs when a byte of data has been received or transmitted by the sim interface. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must frst be set. when the interrupt is enabled, the st ack i s not full a nd a byt e of da ta ha s be en t ransmitted or re ceived by t he sim i nterface, a subroutine call to the respective interrupt vector , will take place. when the serial interface interrupt is service d, the sim interrupt request fag, si m f, will be automatically cleared and the emi bit will be automatically cleared to disable other interrupts. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/ d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector a ddress, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt fag to be set high and consequent ly generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function. rev. 1.00 100 ? a ? 0 ?? ? 01 ? rev. 1.00 101 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. application circuits rev. 1.00 100 ?a? 0?? ?01? rev. 1.00 101 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. rev. 1.00 10 ? ? a ? 0 ?? ? 01 ? rev. 1.00 10? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction set . as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. howeve r, whe n working wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. rev. 1.00 10? ?a? 0?? ?01? rev. 1.00 10 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add data ? emor ? to acc 1 z ? c ? ac ? ov add ? a ? [m] add acc to data ? emor ? 1 note z ? c ? ac ? ov add a ? x add immediate data to acc 1 z ? c ? ac ? ov adc a ? [m] add data ? emor ? to acc with carr ? 1 z ? c ? ac ? ov adc ? a ? [m] add acc to data memor ? with carr ? 1 note z ? c ? ac ? ov sub a ? x subtract immediate data from the acc 1 z ? c ? ac ? ov sub a ? [m] subtract data ? emor ? from acc 1 z ? c ? ac ? ov sub ? a ? [m] subtract data ? emor ? from acc with result in data ? emor ? 1 note z ? c ? ac ? ov sbc a ? [m] subtract data ? emor ? from acc with carr ? 1 z ? c ? ac ? ov sbc ? a ? [m] subtract data ? emor ? from acc with carr ?? result in data ? emor ? 1 note z ? c ? ac ? ov daa [m] decimal adjust acc for addition with result in data ? emor ? 1 note c logic operation and a ? [m] logical and data ? emor ? to acc 1 z or a ? [m] logical or data ? emor ? to acc 1 z xor a ? [m] logical xor data ? emor ? to acc 1 z and ? a ? [m] logical and acc to data ? emor ? 1 note z or ? a ? [m] logical or acc to data ? emor ? 1 note z xor ? a ? [m] logical xor acc to data ? emor ? 1 note z and a ? x logical and immediate data to acc 1 z or a ? x logical or immediate data to acc 1 z xor a ? x logical xor immediate data to acc 1 z cpl [m] complement data ? emor ? 1 note z cpla [m] complement data ? emor ? with result in acc 1 z increment & decrement inca [m] increment data ? emor ? with result in acc 1 z inc [m] increment data ? emor ? 1 note z deca [m] decrement data ? emor ? with result in acc 1 z dec [m] decrement data ? emor ? 1 note z rotate rra [m] rotate data ? emor ? right with result in acc 1 none rr [m] rotate data ? emor ? right 1 note none rrca [m] rotate data ? emor ? right through carr ? with result in acc 1 c rrc [m] rotate data ? emor ? right through carr ? 1 note c rla [m] rotate data ? emor ? left with result in acc 1 none rl [m] rotate data ? emor ? left 1 note none rlca [m] rotate data ? emor ? left through carr ? with result in acc 1 c rlc [m] rotate data ? emor ? left through carr ? 1 note c rev. 1.00 104 ? a ? 0 ?? ? 01 ? rev. 1.00 105 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu mnemonic description cycles flag affected data move ? ov a ? [m] ? ove data ? emor ? to acc 1 none ? ov [m] ? a ? ove acc to data ? emor ? 1 note none ? ov a ? x ? ove immediate data to acc 1 none bit operation clr [m].i clear bit of data ? emor ? 1 note none set [m].i set bit of data ? emor ? 1 note none branch j ? p addr jump unconditionall ? ? none sz [m] skip if data ? emor ? is zero 1 note none sza [m] skip if data ? emor ? is zero with data movement to acc 1 note none sz [m].i skip if bit i of data ? emor ? is zero 1 note none snz [m].i skip if bit i of data ? emor ? is not zero 1 note none siz [m] skip if increment data ? emor ? is zero 1 note none sdz [m] skip if decrement data ? emor ? is zero 1 note none siza [m] skip if increment data ? emor ? is zero with result in acc 1 note none sdza [m] skip if decrement data ? emor ? is zero with result in acc 1 note none call addr subroutine call ? none ret return from subroutine ? none ret a ? x return from subroutine and load immediate data to acc ? none reti return from interrupt ? none table read tabrdc [m] read table to tblh and data ? emor ? ? note none tabrdl [m] read table (last page) to tblh and data ? emor ? ? note none miscellaneous nop no operation 1 none clr [m] clear data ? emor ? 1 note none set [m] set data ? emor ? 1 note none clr wdt clear watchdog timer 1 to ? pdf clr wdt1 pre-clear watchdog timer 1 to ? pdf clr wdt ? pre-clear watchdog timer 1 to ? pdf swap [m] swap nibbles of data ? emor ? 1 note none swapa [m] swap nibbles of data ? emor ? with result in acc 1 none halt enter power down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. f or the " clr wd t1" and " clr wd t2" ins tructions the t o and p df flags may be af fected by the execution status. the t o and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged. rev. 1.00 104 ?a? 0?? ?01? rev. 1.00 105 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z rev. 1.00 106 ? a ? 0 ?? ? 01 ? rev. 1.00 107 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z rev. 1.00 106 ?a? 0?? ?01? rev. 1.00 107 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z rev. 1.00 108 ? a ? 0 ?? ? 01 ? rev. 1.00 109 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none rev. 1.00 108 ?a? 0?? ?01? rev. 1.00 109 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rev. 1.00 110 ? a ? 0 ?? ? 01 ? rev. 1.00 111 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none rev. 1.00 110 ?a? 0?? ?01? rev. 1.00 111 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c rev. 1.00 11 ? ? a ? 0 ?? ? 01 ? rev. 1.00 11 ? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none rev. 1.00 11 ? ?a? 0?? ?01? rev. 1.00 11 ? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z rev. 1.00 114 ? a ? 0 ?? ? 01 ? rev. 1.00 115 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information ? pb free products ? green packages products rev. 1.00 114 ?a? 0?? ?01? rev. 1.00 115 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.01 ? 0.0 ? 0 c 0. ? 86 0. 40 ? d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0.51 c 9.80 10. ? 1 d 1.75 e 1. ? 7 f 0.10 0. ? 5 g 0.41 1. ? 7 h 0.18 0. ? 5 0 8 rev. 1.00 116 ? a ? 0 ?? ? 01 ? rev. 1.00 117 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu 16-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. min. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c 0.189 0.197 d 0.054 0.060 e 0.0 ? 5 f 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. min. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c 4.80 5.00 d 1. ? 7 1.5 ? e 0.64 f 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 0 8 rev. 1.00 116 ?a? 0?? ?01? rev. 1.00 117 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0. ? 9 ? 0.419 b 0. ? 56 0. ? 00 c 0.01 ? 0.0 ? 0 c 0.496 0.51 ? d 0.104 e 0.050 f 0.004 0.01 ? g 0.016 0.050 h 0.008 0.01 ? 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.6 ? c 0. ? 0 0.51 c 1 ? .60 1 ? .00 d ? .64 e 1. ? 7 f 0.10 0. ? 0 g 0.41 1. ? 7 h 0. ? 0 0. ?? 0 8 rev. 1.00 118 ? a ? 0 ?? ? 01 ? rev. 1.00 119 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.158 c 0.008 0.0 1 ? c 0. ?? 5 0. ? 47 d 0.049 0.065 e 0.0 ? 5 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 4.01 c 0. ? 0 0. ? 0 c 8.51 8.81 d 1. ? 4 1.65 e 0.64 f 0.10 0. ? 5 g 0. ? 8 1. ? 7 h 0.18 0. ? 5 0 8 rev. 1.00 118 ?a? 0?? ?01? rev. 1.00 119 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu 24-pin sop (300mil) outline dimensions ms-0 13 symbol dimensions in inch min. nom. min. a 0. ? 9 ? 0.419 b 0. ? 56 0. ? 00 c 0.01 ? 0.0 ? 0 c 0.598 0.61 ? d 0.104 e 0.050 f 0.004 0.01 ? g 0.016 0.050 h 0.008 0.01 ? 0 8 symbol dimensions in mm min. nom. min. a 9.98 10.64 b 6.50 7.6 ? c 0. ? 0 0.51 c 15.19 15.57 d ? .64 e 1. ? 7 f 0.10 0. ? 0 g 0.41 1. ? 7 h 0. ? 0 0. ?? 0 8 rev. 1.00 1 ? 0 ? a ? 0 ?? ? 01 ? rev. 1.00 1?1 ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. min. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c 0. ?? 5 0. ? 46 d 0.054 0.060 e 0.0 ? 5 f 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. min. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c 8.51 8.79 d 1. ? 7 1.5 ? e 0.64 f 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 0 8 rev. 1.00 1?0 ?a? 0?? ?01? rev. 1.00 1 ? 1 ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. min. a 0. ? 9 ? 0.419 b 0. ? 56 0. ? 00 c 0.01 ? 0.0 ? 0 c 0.697 0.71 ? d 0.104 e 0.050 f 0.004 0.01 ? g 0.016 0.050 h 0.008 0.01 ? 0 8 symbol dimensions in mm min. nom. min. a 9.98 10.64 b 6.50 7.6 ? c 0. ? 0 0.51 c 17.70 18.11 d ? .64 e 1. ? 7 f 0.10 0. ? 0 g 0.41 1. ? 7 h 0. ? 0 0. ?? 0 8 rev. 1.00 1 ?? ? a ? 0 ?? ? 01 ? rev. 1.00 1?? ?a? 0?? ?01? BS84B08A-3/bs84c12a-3 a/d type touch key mcu 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. min. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c 0. ? 86 0. ? 94 d 0.054 0.060 e 0.0 ? 5 f 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. min. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c 9.80 10.01 d 1. ? 7 1.5 ? e 0.64 f 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 0 8 rev. 1.00 1?? ?a? 0?? ?01? rev. 1.00 1 ?? ? a ? 0 ?? ? 01 ? BS84B08A-3/bs84c12a-3 a/d type touch key mcu cop ? right ? ? 01 ? b ? holtek se ? iconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however ? holtek assumes no responsibilit ? arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warrant ? or representation that such applications will be suitable without further modification ? nor recommends the use of its products for application that ma ? present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or s ? stems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com. |
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